TLC34076 datasheet(28/68 Pages) TI

28 / 68 page

2–12

Since this mode is designed with the feature connector philosophy, all the timing is referenced to CLK0,

which is used by default for the VGA pass-through mode. For all the other normal modes, CLK0 – CLK3 are

the oscillator sources for DOTCLK, VCLK, and SCLK; all the data and control timing is referenced to SCLK.

2.4.2

Multiplexing Modes

In addition to the VGA pass-through mode, there are four multiplexing modes available, all of which are

referred to as normal modes. In each normal mode, a pixel bus width of 8, 16, or 32 bits may be used. Modes

1, 2, and 3 also support a pixel bus width of 4 bits. Data should always be presented on the least significant

bits of the pixel bus. For example, when a 16-bit-wide pixel bus is used and there are 8 bits per pixel, each

8-bit pixel should be presented on P0 – P7. All the unused pixel bus terminals should be connected to GND.

Mode 1 uses a single bit-plane to address the color palette. The pixel port bit is fed into bit 0 of the palette

address, with the seven high-order address bits being defined by the palette page register (see subsection

2.2.3). This mode has uses in high-resolution monochrome applications such as desktop publishing. This

mode allows the maximum amount of multiplexing (a 32:1 ratio), thus giving a pixel bus rate of only 4 MHz

at a screen resolution of 1280

1024 pixels. Although only a single-bit plane is used, alteration of the palette

page register at the line frequency allows 256 different colors to be displayed simultaneously with two colors

per line.

Mode 2 uses two bit-planes to address the color palette. The 2 bits are fed into the low-order address bits

of the palette with the six high-order address bits being defined by the palette page register. This mode

allows a maximum divide ratio of 16:1 on the pixel bus and is a 4-color alternative to mode 1.

Mode 3 uses four bit-planes to address the color palette. The 4 bits are fed into the low-order address bits

of the palette with the four high-order address bits being defined by the palette page register. This mode

provides 16 pages of 16 colors and can be used at SCLK divide ratios of 1:8.

Mode 4 uses eight bit-planes to address the color palette. Since all 8 bits of palette address are specified

from the pixel port, the page register is not used. This mode allows dot-clock-to-SCLK ratios of 1:1 (8-bit

bus), 2:1 (16-bit bus) or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024

768 pixel screen can

be implemented with an external data rate of only 16 MHz.

All normal multiplexing modes can support little-endian (default) and big-endian data formats at the pixel

bus inputs (see subsection 2.6.1).

2.4.3

Special Nibble Mode

Mode 5 is the special nibble mode, which is enabled when the general-control register SNM bit 3 is set to

1 and the general-control register SSRT bit 2 is cleared to 0 (see Section 2.11). When the special nibble

mode is enabled, it takes precedence over the other modes, and the mux control register setup is ignored.

The SFLAG/NFLAG input is then used as a nibble flag to indicate which nibble of each byte holds the pixel

data. Special-nibble mode is a variation of the 4-bit pixel mode with a 16-bit pixel width. All 32 inputs

(P0

*P31) are connected as four bytes, but the 16-bit data bus is composed of either the lower or upper

nibble of each of the four bytes (for more detailed information, see subsection 2.9.2). Since this mode uses

four bit-planes for each pixel, they are fed into the low-order address bits of the palette, with the 4 high-order

address bits being defined by the palette page register (see subsection 2.2.3).

2.4.4

True-Color Modes

Mode 6 is the true-color mode in which 24, 16, or 15 bits of data are transferred from the pixel port directly

to the DACs, but with the same amount of pipeline delay as the overlay data and the control signals (BLANK

and Sync). Depending on which true-color mode is selected, overlay is provided by utilizing the remaining

bits of the pixel bus to address the palette RAM (see Tables 2–6 and 2–7). This results in a 24-bit RAM output

that is then used as overlay information to the DACs. When all of the overlay inputs are cleared to 0, no

overlay information is displayed. When a nonzero value is input, the color palette RAM is addressed and

the resulting data is then fed through to the DACs and receives priority over the true-color data.

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