Page 2-4
Chapter 2. EZ-USB CPU
EZ-USB TRM v1.9
•
An output enable bit that causes the IO pin to be driven from the output latch.
•
An alternate function bit that determines whether the pin is general IO or a special
8051 or EZ-USB function.
The SFRs associated with 8051 ports 0-3 are not implemented in EZ-USB. These SFR
addresses include P0 (0x80), P1 (0x90), P2 (0xA0), and P3 (0xB0). Because P2 is not
implemented, the MOVX@R0/R1 instruction takes the upper address byte from an added
Special Function Register (SFR) at location 0x92. This register is called “MPAGE” in the
Appendices.
All standard 8051 interrupts are supported in the enhanced 8051 core. Table 2-1 shows
the existing and added 8051 interrupts, and indicates how the added ones are used.
The EZ-USB chip uses 8051 INT2 for 21 different USB interrupts: 16 bulk endpoints plus
SOF, Suspend, SETUP Data, SETUP Token, and USB Bus Reset. To help the 8051 deter-
mine which interrupt is active, the EZ-USB core provides a feature called Autovectoring.
The core inserts an address byte into the low byte of the 3-byte jump instruction found at
the 8051 INT2 vector address. This second level of vectoring automatically transfers con-
trol to the appropriate USB ISR. The Autovector mechanism, as well as the EZ-USB
interrupt system is the subject of Chapter 9, "EZ-USB Interrupts."
2.7
Interrupts
Table 2-1. EZ-USB Interrupts
Standard 8051
Interrupts
Enhanced 8051
Interrupts
Used As
INT0
Device Pin INT0#
INT1
Device Pin INT1#
Timer 0
Internal, Timer 0
Timer 1
Internal, Timer 1
Tx0 & Rx0
Internal, UART0
INT2
Internal, USB
INT3
Internal, I2C Controller
INT4
Device Pin, PB4/INT4
INT5
Device Pin, PB5/INT5#
INT6
Device Pin, PB6/INT6
PF1
Device Pin, USB WAKEUP#
Tx1 & Rx1
Internal, UART1
Timer 2
Internal, Timer 2
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