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SC2200 Datasheet(PDF) 194 Page - National Semiconductor (TI) |
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SC2200 Datasheet(HTML) 194 Page - National Semiconductor (TI) |
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194 / 433 page  www.national.com 194 Revision 3.0 Core Logic Module (Continued) Table 5-24. F5: PCI Header Registers for X-Bus Expansion Support Summary F5 Index Width (Bits) Type Name Reset Value Reference (Table 5-39) 00h-01h 16 RO Vendor Identification Register 100Bh Page 283 02h-03h 16 RO Device Identification Register 0505h Page 283 04h-05h 16 R/W PCI Command Register 0000h Page 283 06h-07h 16 RO PCI Status Register 0280h Page 283 08h 8 RO Device Revision ID Register 00h Page 283 09h-0Bh 24 RO PCI Class Code Register 068000h Page 283 0Ch 8 RO PCI Cache Line Size Register 00h Page 283 0Dh 8 RO PCI Latency Timer Register 00h Page 283 0Eh 8 RO PCI Header Type Register 00h Page 283 0Fh 8 RO PCI BIST Register 00h Page 283 10h-13h 32 R/W Base Address Register 0 (F5BAR0) — Sets the base address for the X-Bus Expansion support registers (summarized in Table 5-25.) 00000000h Page 283 14h-17h 32 R/W Base Address Register 1 (F5BAR1) — Reserved for possible future use by the Core Logic module. 00000000h Page 283 18h-1Bh 32 R/W Base Address Register 2 (F5BAR2) — Reserved for possible future use by the Core Logic module. 00000000h Page 283 1Ch-1Fh 32 R/W Base Address Register 3 (F5BAR3) — Reserved for possible future use by the Core Logic module. 00000000h Page 283 20h-23h 32 R/W Base Address Register 4 (F5BAR4) — Reserved for possible future use by the Core Logic module. 00000000h Page 284 24h-27h 32 R/W Base Address Register 5 (F5BAR5) — Reserved for possible future use by the Core Logic module. 00000000h Page 284 28h-2Bh --- --- Reserved 00h Page 284 2Ch-2Dh 16 RO Subsystem Vendor ID 100Bh Page 284 2Eh-2Fh 16 RO Subsystem ID 0505h Page 284 30h-3Fh --- --- Reserved 00h Page 284 40h-43h 32 R/W F5BAR0 Base Address Register Mask FFFFFFC1h Page 284 44h-47h 32 R/W F5BAR1 Base Address Register Mask 00000000h Page 284 48h-4Bh 32 R/W F5BAR2 Base Address Register Mask 00000000h Page 285 4Ch-4Fh 32 R/W F5BAR3 Base Address Register Mask 00000000h Page 285 50h-53h 32 R/W F5BAR4 Base Address Register Mask 00000000h Page 285 54h-57h 32 R/W F5BAR5 Base Address Register Mask 00000000h Page 285 58h 8 R/W F5BARx Initialized Register 00h Page 285 59h-FFh --- --- Reserved xxh Page 285 60h-63h 32 R/W Scratchpad for Chip Number 00000000h Page 285 64h-67h 32 R/W Scratchpad for Configuration Block Address 00000000h Page 285 68h-FFh --- --- Reserved --- Page 285 Table 5-25. F5BAR0: I/O Control Support Registers Summary F5BAR0+ I/O Offset Width (Bits) Type Name Reset Value Reference (Table 5-40) 00h-03h 32 R/W I/O Control Register 1 010C0007h Page 286 04h-07h 32 R/W I/O Control Register 2 00000002h Page 286 08h-0Bh 32 R/W I/O Control Register 3 00009000h Page 287 |
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