PC97307 datasheet(72/218 Pages) NSC

72 / 218 page

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

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TABLE 5-2. Drive and Motor Pin Encoding for Four

Drive Conﬁgurations and Drive Exchange Support

Usually, the motor enable and drive select output signals for

a particular drive are enabled together. Table 5-3 shows the

DOR hexadecimal values that enable each of the four

drives.

TABLE 5-3. Drive Enable Hexadecimal Values

The motor enable and drive select signals for drives 2 and

3 are only available when four drives are supported, i.e., bit

7 of the SuperI/O FDC Configuration register at index F0h

is 1, or when drives 2 and 0 are exchanged. These signals

require external logic.

Digital Output

Control

Signals

Decoded Functions

MTR DR

765432101010

x x x1x x0 0 - 0 0 0

Activate Drive 0

and Motor 0

x x 1 x x x 0 1-0 0 1

Activate Drive 1

and Motor 1

x1x x x x1 0 - 0 1 0

Activate Drive 2

and Motor 2

1x x x x x1 1 - 0 1 1

Activate Drive 3

and Motor 3

x x x0x x0 0 - 1 0 0

Activate Drive 0 and

Deactivate Motor 0

x x 0 x x x 0 1-1 0 1

Activate Drive 1 and

deactivate Motor 1

x0x x x x1 0 - 1 1 0

Activate Drive 2 and

Deactivate Motor 2

0x x x x x1 1 - 1 1 1

Activate Drive 3 and

Deactivate Motor 3

Drive

DOR Value (Hex)

01C

12D

24E

38F

FIGURE 5-7. DOR Register Bitmap

Bits 1,0 - Drive Select

These bits select a drive, so that only one drive select

output signal is active at a time.

See the four-drive encoding bit 7 of the SuperI/O FDC

Configuration register at index F0h on page 37 and log-

ical drive exchange bits 3,2 of TDR on page 74 for more

information.

00 - Drive 0 is selected. (Default)

01 - Drive 1 is selected.

10 - If four drives are supported, or drives 2 and 0 are

exchanged, drive 2 is selected.

11 - If four drives are supported, drive 3 is selected.

Bit 2 - Reset Controller

This bit can cause a software reset. The controller re-

mains in a reset state until this bit is set to 1.

A software reset affects the CONFIGURE and MODE

commands. See Section 5.7.2 on page 88 and 5.7.7 on

page 92, respectively. A software reset does not affect

the Data rate Select Register (DSR), Configuration Con-

trol Register (CCR) and other bits of this register (DOR).

This bit must be low for at least 100 nsec. There is

enough time during consecutive writes to the DOR to re-

set software by toggling this bit.

0 - Reset controller. (Default)

1 - No reset.

Bit 3 - DMA Enable (DMAEN)

In PC-AT drive mode, this bit enables DMA operations

by controlling DACK, TC and the appropriate DRQ and

IRQ DMA signals. In PC-AT mode, this bit is set to 0 af-

ter reset.

In PS/2 drive mode, this bit is reserved, and DACK, TC

and the appropriate DRQ and IRQ signals are enabled.

During reset, these signals remain enabled.

0 - In PC-AT drive mode, DMA operations are dis-

abled. DACK and TC are disabled, and the appro-

priate DRQ and IRQ signals are put in TRI-STATE.

(Default)

1 - In PC-AT drive mode, DMA operations are enabled,

i.e., DACK, TC and the appropriate DRQ and IRQ

signals are all enabled.

76543210

Reset

Required

Digital Output

Offset 02h

Reset Controller

Motor Enable 0

Motor Enable 1

Motor Enable 2

Motor Enable 3

Drive Select

DMAEN

PC97307 Datasheet(PDF) 72 Page - National Semiconductor (TI)

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