PC97307 datasheet(10/218 Pages) NSC

10 / 218 page

Table of Contents

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7.2.3

Consumer IR Mode ................................................................................................... 135

7.3

REGISTER BANK OVERVIEW ............................................................................................... 136

7.4

UART MODES – DETAILED DESCRIPTION .......................................................................... 136

7.4.1

16450 or 16550 UART Mode ..................................................................................... 137

7.4.2

Extended UART Mode ............................................................................................... 137

7.5

SHARP-IR MODE – DETAILED DESCRIPTION ..................................................................... 138

7.6

SIR MODE – DETAILED DESCRIPTION ................................................................................ 138

7.7

CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................ 138

7.7.1

Consumer-IR Transmission ....................................................................................... 138

7.7.2

Consumer-IR Reception ............................................................................................ 138

7.8

FIFO TIME-OUTS .................................................................................................................... 139

7.8.1

UART, SIR or Sharp-IR Mode Time-Out Conditions ................................................. 139

7.8.2

Consumer-IR Mode Time-Out Conditions ................................................................. 139

7.8.3

Transmission Deferral ............................................................................................... 139

7.9

AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE .......................................... 140

7.10

OPTICAL TRANSCEIVER INTERFACE ................................................................................. 140

7.11

BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS ................................................. 140

7.11.1

Receiver Data Port (RXD) or the Transmitter Data Port (TXD), Bank 0, Offset 00h . 141

7.11.2

Interrupt Enable Register (IER), Bank 0, Offset 01h ................................................. 141

7.11.3

Event Identification Register (EIR), Bank 0, Offset 02h ............................................. 143

7.11.4

FIFO Control Register (FCR), Bank 0, Offset 02h ..................................................... 145

7.11.5

Link Control Register (LCR), Bank 0, Offset 03h, and Bank Selection Register (BSR),

All Banks, Offset 03h ........................................................................................... 145

7.11.6

Bank Selection Register (BSR), All Banks, Offset 03h .............................................. 147

7.11.7

Modem/Mode Control Register (MCR), Bank 0, Offset 04h ...................................... 147

7.11.8

Link Status Register (LSR), Bank 0, Offset 05h ........................................................ 148

7.11.9

Modem Status Register (MSR), Bank 0, Offset 06h .................................................. 149

7.11.10 Scratchpad Register (SPR), Bank 0, Offset 07h ....................................................... 150

7.11.11 Auxiliary Status and Control Register (ASCR), Bank 0, Offset 07h ........................... 150

7.11.12 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)),

Bank 1, Offsets 00h and 01h ............................................................................... 151

7.11.13 Link Control Register (LCR) and Bank Select Register (BSR), Bank 1, Offset 03h .. 152

7.12

BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................ 152

7.12.1

Baud Generator Divisor Ports, LSB (BGD(L)) and

MSB (BGD(H)),Bank 2, Offsets 00h and 01h ...................................................... 152

7.12.2

Extended Control Register 1 (EXCR1), Bank 2, Offset 02h ...................................... 154

7.12.3

Link Control Register (LCR) and Bank Select Register (BSR), Bank 2, Offset 03h .. 155

7.12.4

Extended Control and Status Register 2 (EXCR2), Bank 2, Offset 04h .................... 155

7.12.5

Reserved Register, Bank 2, Offset 05h ..................................................................... 155

7.12.6

TX_FIFO Current Level Register (TXFLV), Bank 2, Offset 06h ................................ 155

7.12.7

RX_FIFO Current Level Register (RXFLV), IrDA or Consumer-IR Modes,

Bank 2, Offset 07h .............................................................................................. 156

7.13

BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 156

7.13.1

Module Revision ID Register (MRID), Bank 3, Offset 00h ......................................... 156

7.13.2

Shadow of Link Control Register (SH_LCR), Bank 3, Offset 01h .............................. 157

PC97307 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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