PC97307 datasheet(75/218 Pages) NSC

75 / 218 page

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

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Bit 2 - Drive 2 Busy

This bit indicates whether or not drive 2 is busy.

It is set to 1 after the last byte of the command phase of

a SEEK or RECALIBRATE command is issued for drive

This bit is cleared to 0 after the first byte in the result

phase of the SENSE INTERRUPT command is read for

drive 2.

0 - Not busy.

1 - Busy.

Bit 3 - Drive 3 Busy

This bit indicates whether or not drive 3 is busy.

It is set to 1 after the last byte of the command phase of

a SEEK or RECALIBRATE command is issued for drive

This bit is cleared to 0 after the first byte in the result

phase of the SENSE INTERRUPT command is read for

drive 3.

0 - Not busy.

1 - Busy.

Bit 4 - Command in Progress

This bit indicates whether or not a command is in

progress. It is set after the first byte of the command

phase is written. This bit is cleared after the last byte of

the result phase is read.

If there is no result phase in a command, the bit is

cleared after the last byte of the command phase is writ-

ten.

0 - No command is in progress.

1 - A command is in progress.

Bit 5 - Non-DMA Execution

This bit indicates whether or not the controller is in the

execution phase of a byte transfer operation in non-

DMA mode.

This bit is used for multiple byte transfers by the micro-

processor in the execution phase through interrupts or

software polling.

0 - The FDC is not in the execution phase.

1 - The FDC is in the execution phase.

Bit 6 - Data I/O (Direction)

Indicates whether the controller is expecting a byte to be

written or read, to or from the Data Register (FIFO).

0 - Data will be written to the FIFO.

1 - Data will be read from the FIFO.

Bit 7 - Request for Master (RQM)

This bit indicates whether or not the controller is ready

to send or receive data from the microprocessor through

the Data Register (FIFO). It is cleared to 0 immediately

after a byte transfer and is set to 1 again as soon as the

disk controller is ready for the next byte.

During a Non-DMA execution phase, this bit indicates

the status of the interrupt.

0 - Not ready. (Default)

1 - Ready to transfer data.

5.3.6

Data Rate Select Register (DSR), Offset 04h,

Write Operations

This write-only register is used to program the data transfer

rate, amount of write precompensation, power down mode,

and software reset.

The data transfer rate is programmed via the CCR, not the

DSR, for PC-AT, PS/2 and MicroChannel applications. Oth-

er applications can set the data transfer rate in the DSR.

The data rate of the floppy controller is determined by the

most recent write to either the DSR or CCR.

The DSR is unaffected by a software reset. A hardware re-

set sets the DSR to 02h, which corresponds to the default

precompensation setting and a data transfer rate of 250

Kbps.

FIGURE 5-11. DSR Register Bitmap

Bits 1,0 - Data Transfer Rate Select

These bits determine the data transfer rate for the Flop-

py Disk Controller (FDC), depending on the supported

speeds. Table 5-6 shows the data transfer rate selected

by each value of this field.

These bits are unaffected by a software reset, and are

set to 10 (250 Kbps) after a hardware reset.

TABLE 5-6. Data Transfer Rate Encoding

Bits 4-2 - Precompensation Delay Select

This field sets the write precompensation delay that the

Floppy Disk Controller (FDC) imposes on the WDATA

disk interface output signal, depending on the supported

speeds. Table 5-7 shows the delay for each value of this

field.

In most cases, the default delays shown in Table 5-8 are

adequate. However, alternate values may be used for

specific drive and media types.

DSR Bits

Data Transfer Rate

500 Kbps

300 Kbps

250 Kbps

1 Mbps

76543210

Reset

Required

Data Rate Select

Offset 04h

Precompensation Delay Select

Undefined

Low Power

Software Reset

Data Transfer Rate Select

Write Operations

PC97307 Datasheet(PDF) 75 Page - National Semiconductor (TI)

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