PC97307 datasheet(171/218 Pages) NSC

171 / 218 page

171

General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals

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TABLE 8-2. The GPIO Registers, Bank 1

GPIO Register

Offset

Type

Hard Reset

Value

Detailed Description

Port 1 Lock

00h

R/W

00h

Bits 5-0 are reserved.

Bits 7,6 lock the Port 1 control settings for bits GPIO17,16,

respectively. Setting them to 1 locks the corresponding pin

direction and pull-up bit settings. When conﬁgured as output, the

pin value and buffer type are also locked.

Only master reset unlocks these bits by setting them to 0s.

Reserved

01h-07h

8.2

PROGRAMMABLE CHIP SELECT OUTPUT

SIGNALS

The part has three programmable chip select signals: CS2-

0. CS0 is an open drain output signal (CS1 and CS2 have

push-pull buffers). CS0 is in TRI-STATE when no VDD is ap-

plied.

Activation and deactivation (enabling and disabling) of

these chip select signals are controlled by the Function En-

able Register 2 (FER2) of logical device 8 (see section 9.2.4

on page 173) and the configuration registers for CS0, CS1

and CS2 at second level indexes 02h, 06h and 0Ah, respec-

tively.

These registers are accessed using two index levels.

The first level index points to the Programmable Chip Select

Index and Data registers, like other part configuration regis-

ters. See Sections 2.4.5 and 2.4.6 on page 36. The Pro-

grammable Chip Select Configuration Index and Data

registers are at index 23h and 24h respectively.

The second level points to one of the three registers for

each CS pin. See “Programmable Chip Select Configura-

tion Registers” on page 39. Each CS pin is configured by

the three registers assigned to it. One specifies the base ad-

dress MSB. One specifies the base address LSB and one

configures the CS pin.

All 16 address bits are decoded, with five mask options to

ignore (not decode) address bits A0, A1, A2, A3 and A4-11.

Decoding of only address and AEN pins, without RD or WR

pins, is also supported.

A CS signal is asserted when an address match occurs and

may be qualified by RD or WR signal(s). An address match

occurs when the AEN signal is inactive (low) and the non-

masked address pins match the corresponding base ad-

dress bits.

PC97307 Datasheet(PDF) 171 Page - National Semiconductor (TI)

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