PC87338 datasheet(50/221 Pages) NSC

50 / 221 page

www.national.com

Bit 3 - ECP Clock Freeze Control

When either this bit or the ECP enable bit is 0,

there is no change in the Chip clock stopping

mechanism.

0 - The ECP does not affect the stopping of the

clock multiplier (power-down mode 3) and

does not change the function of bit 0 of PTR.

1 - If the ECP is enabled (bit 2 of PCR is 1), the

clock multiplier is not stopped (power mode 3

is not entered) and the ECP clock is not

stopped (power down mode 2 excludes the

ECP).

Bit 4 - Reserved

This bit is reserved and must be set to 0.

Bit 5 - Parallel Port Interrupt Polarity Control

This bit controls the polarity of the interrupt line al-

located for the parallel port.

0 - The interrupt polarity is as defined in the exist-

ing Chip, and the ECP interrupt event is level

high or negative pulse.

1 - The interrupt event polarity is inverted.

Bit 6 - Parallel Port Open-Drain Control

Parallel port interrupt (the parallel port-allocated

interrupt line) open-drain control bit.

0 - The configured interrupt line (IRQ5 or IRQ7)

has a totem-pole output with TRI-STATE abili-

ty.

1 - The configured interrupt line has an open

drain output signal (drive low or TRI-STATE).

Bit 7 - Reserved

This bit is reserved. To maintain compatibility with

future Super I/O chips, do not modify this bit when

this register is written, i.e., use read-modify-write

to preserve the value of this bit.

2.3.7

Power Management Control

This register controls the TRI-STATE and input sig-

nals. The PMC Register is accessed at index 06h.

The PMC Register is cleared to 0 on reset.

FIGURE 8. PMC Register Bitmap

Bit 0 - Reserved

This bit is reserved.

Bit 1 - FDC TRI-STATE Control

0 - No TRI-STATE enabled.

1 - If the FDC is powered down, the FDC output

signals are in TRI-STATE, except the FDC-al-

located interrupt line, PD, IDLE and the PPM

output signals, even if the PPM is used for

FDC pins, i.e., this bit does not control the

IRQ6 and PPM pins.

In addition, if the FDC is powered down, the

FDC input signals (except DSKCHG) are

blocked to reduce their leakage current.

Bit 2 - SCC1 TRI-STATE Control

This bit controls the TRI-STATE status of the

SCC1 output pins and blocked the input pins, to

avoid leakage current. This bit does not control the

TRI-STATE status of the SCC1 interrupt.

0 - TRI-STATE disabled on SCC1 signals.

1 - If SCC1 is disabled or the Chip is in power-

down mode, SCC1 output signals are in TRI-

STATE and the input signals are blocked to

reduce their leakage current.

The values of the blocked input signals are:

SIN1=1, CTS1=1, DSR1=1, DCD1=1 and

RI1=1.

Bit 3 - Reserved

This bit is reserved.

543

(PMC)

Reset

Required

Power Management

Index 06h

Control Register

Reserved

FDC TRI-STATE Control

SCC1 TRI-STATE Control

Reserved

PD and IDLE or IRSL2/ID2 Enable

Selective Lock

PPM TRI-STATE Enable

Reserved

PC87338 Datasheet(PDF) 50 Page - National Semiconductor (TI)

PC87338 Datasheet(HTML) 50 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL