PC87360 datasheet(136/168 Pages) NSC

136 / 168 page

8.0 ACCESS.bus Interface (ACB) (Continued)

136

www.national.com

8.3.5

ACB Control Register 1 (ACBCTL1)

Location:

Offset 03h

Type:

R/W

Bit

76543210

Name

STASTRE

NMINTE

GCMEN

ACK

Reserved

INTEN

STOP

START

Reset

00000000

Bit

Description

STASTRE (Stall After Start Enable)

0: When cleared, ACBST.STASTR can not be set. However, if ACBST.STASTR is set, clearing STASTRE will not

clear ACBST.STASTR.

1: Stall after start mechanism enabled, and ACB stalls the bus after the address byte

NMINTE (New Match Interrupt Enable)

0: No interrupt issued on a new match

1: Interrupt issued on a new match only if ACBCTL1.INTEN set

GCMEN (Global Call Match Enable)

0: ACB not responding to global call

1: Global call match enabled

Receive Acknowledge. This bit is ignored in transmit mode. When the device acts as a receiver (slave or

master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle.

0: Cleared after acknowledge cycle

1: Negative acknowledge issued on next received byte

Reserved

Interrupt Enable

0: ACB interrupt disabled

1: ACB interrupt enabled. An interrupt is generated in response to one of the following events:

—

Detection of an address match (ACBST.NMATCH=1) and NMINTE=1

—

Receipt of Bus Error (ACBST.BER=1)

—

Receipt of Negative Acknowledge after sending a byte (ACBST.NEGACK=1)

—

Acknowledge of each transaction (same as the hardware set of the ACBST.SDAST bit)

—

In master mode if ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1)

—

Detection of a Stop Condition while in slave mode (ACBST.SLVSTP=1).

Stop

0: Automatically cleared after STOP issued

1: Setting this bit in master mode generates a Stop Condition to complete or abort current message transfer

Start. Set this bit only when in master mode or when requesting master mode.

0: Cleared after Start Condition sent or Bus Error (ACBST.BER=1) detected

1: Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master of

the bus (ACBST.MASTER=0), setting START generates a Start Condition when the ACCESS.bus becomes

free (ACBCST.BB=0). An address transmission sequence should then be performed.

If the device is the active master of the bus (ACBST.MASTER=1), setting START and then writing to the

ACBSDA register generates a Start Condition. If a transmission is already in progress, a repeated Start

Condition is generated. This condition can be used to switch the direction of the data ﬂow between the master

and the slave, or to choose another slave device without separating them with a Stop Condition.

PC87360 Datasheet(PDF) 136 Page - National Semiconductor (TI)

PC87360 Datasheet(HTML) 136 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL