ST7260XX datasheet(61/139 Pages) STMICROELECTRONICS

61 / 139 page

ST7260xx

Watchdog timer (WDG)

61/139

Figure 37.

Pulse width modulation cycle

If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the

OC2R and OC1R registers.

If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.

The OC1R register value required for a specific timing application can be calculated using

the following formula:

Where:

= Signal or pulse period (in seconds)

fCPU

= CPU clock frequnency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 32)

If the timer clock is an external clock the formula is:

Where:

= Signal or pulse period (in seconds)

fEXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 36).

Note:

After a write instruction to the OCiHR register, the output compare function is inhibited until

the OCiLR register is also written.

The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be

set and IC2R can be loaded) but the user must take care that the counter is reset each

period and ICF1 can also generates interrupt if ICIE is set.

When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

counter

OCMP1 = OLVL2

counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

counter is reset

to FFFCh

ICF1 bit is set

OCiR value =

t * fCPU

PRESC

- 5

OCiR = t * fEXT - 5

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