ST7260XX datasheet(41/139 Pages) STMICROELECTRONICS

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ST7260xx

I/O ports

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Figure 22.

Port C configuration

10.2.4

10.2.5

Data register (PxDR)

DDR

LATCH

DR SEL

DDR SEL

VDD

PAD

ALTERNATE ENABLE

ALTERNATE

ALTERNATE INPUT

PULL-UP

OUTPUT

P-BUFFER

N-BUFFER

CMOS SCHMITT TRIGGER

VSS

VDD

DIODES

PADR

PBDR

PCDR

Reset value: 0000 0000 (00h)

Reset value: 1111 x000 (Fxh)

543

R/W

Table 18.

PxDR register description

Bit

Name

Function

7:0

D[7:0]

Data bits

The DR register has a specific behavior according to the selected input/output

configuration. Writing the DR register is always taken into account even if the pin is

configured as an input. Reading the DR register returns either the DR register latch

content (pin configured as output) or the digital value applied to the I/O pin (pin

configured as input).

– When using open-drain I/Os in output configuration, the value read in DR is the

digital value applied to the I/O pin.

– For Port C, unused bits (7-3) are not accessible

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