ST7260XX datasheet(76/139 Pages) STMICROELECTRONICS

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Serial communications interface (SCI)

ST7260xx

76/139

Note:

Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in

the SCIDR.

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9

bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this

mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the

received shift register (see <Blue HT>Figure 38).

Procedure

●

Select the M bit to define the word length.

●

Select the desired baud rate using the SCIBRR and the SCIERPR registers.

●

Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

●

The RDRF bit is set. It indicates that the content of the shift register is transferred to the

RDR.

●

An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

●

The error flags can be set if a frame error, noise or an overrun error has been detected

during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

An access to the SCISR register

A read to the SCIDR register

The RDRF bit must be cleared before the end of the reception of the next character to avoid

an overrun error.

Break Character

When a break character is received, the SCI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character

plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data

can not be transferred from the shift register to the RDR register as long as the RDRF bit is

not cleared.

When a overrun error occurs:

●

The OR bit is set.

●

The RDR content will not be lost.

●

The shift register will be overwritten.

●

An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read

operation.

ST7260XX Datasheet(PDF) 76 Page - STMicroelectronics

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