TUSB544 datasheet(36/60 Pages) TI1

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TUSB544

SLLSEZ0B – APRIL 2017 – REVISED MAY 2017

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7.6.1.8 DISPLAYPORT_5 Register (Offset = 1Bh) [reset = 0h]

DISPLAYPORT_5 is shown in Figure 29 and described in Table 20.

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Figure 29. DISPLAYPORT_5 Register

I2C_RST

DPCD_RST

Table 20. DISPLAYPORT_5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

I2C_RST

Resets I2C registers to default values. This field is self- clearing.

3-0

DPCD_RST

Resets DPCD registers to default values. This field is self- clearing.

7.6.1.9 USB3.1_1 Register (Offset = 20h) [reset = 0h]

USB3.1 is shown in Figure 30 and described in Table 21.

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Figure 30. USB3.1 Register

DTX2EQ_SEL

DRX2EQ_SEL

R/WU-0h

Table 21. USB3.1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

DTX2EQ_SEL

R/WU

Field selects between 0 to 11 dB of EQ for DTX2P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

DEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for DTX2P/N pins based on value written to this field.

3-0

DRX2EQ_SEL

R/WU

Field selects between 0 to 11 dB of EQ for DRX2P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

DEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for DRX2P/N pins based on value written to this field.

TUSB544 Datasheet(PDF) 36 Page - Texas Instruments

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