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TLV809 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV809 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 22 page ![]() t d t d t 1 0 t RESET ForV <1.1VUndefined BehaviorofOutput DD RESET 1.1V V DD V IT- TLV803, TLV853, TLV863 www.ti.com SBVS157C – APRIL 2011 – REVISED SEPTEMBER 2015 7.5 Electrical Characteristics over recommended operating junction temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 2 V to 6 V, IOL = 500 µA 0.2 VOL Low-level output voltage VDD = 3.3 V, IOL = 2 mA 0.4 V VDD = 6 V, IOL = 4 mA 0.4 Power-up reset voltage(1) IOL = 50 µA, VOL < 0.2 V 1.1 V TLV803Z 2.20 2.25 2.30 TLV803R 2.58 2.64 2.70 Negative-going input VIT– TJ = – 40°C to +125°C V threshold voltage(2) TLV803S 2.87 2.93 2.99 TLV8x3M 4.28 4.38 4.48 TLV803Z 30 TLV803R 35 Vhys Hysteresis TJ = 25°C, IOL = 50 µA mV TLV803S 40 TLV8x3M 60 VDD = 2 V, output unconnected 9 15 IDD Supply current µA VDD = 6 V, output unconnected 20 30 IOH Output leakage current VDD = 6 V 100 nA (1) The lowest supply voltage at which RESET becomes valid. tr,VDD ≤ 66.7 V/ms. (2) To ensure best stability of the threshold voltage, place a bypass capacitor (0.1-µF ceramic) near the supply terminals. 7.6 Switching Characteristics over operating temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw Pulse duration at VDD VDD = 1.08 VIT– to 0.92 VIT– 1 µs td Delay time VDD ≥ VIT– + 0.2 V; see Timing Diagram 120 200 280 ms Figure 1. Timing Diagram Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TLV803 TLV853 TLV863 |
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