LMT86LP datasheet(15/30 Pages) TI1

15 / 30 page

LMT86, LMT86-Q1

www.ti.com

SNIS169C – MARCH 2013 – REVISED OCTOBER 2015

Typical Applications (continued)

9.2.2.2 Detailed Design Procedure

Simply connect the VDD pin of the LMT86 directly to the logic shutdown signal from a microcontroller.

9.2.2.3 Application Curves

Time: 500 µsec/div; Top Trace: VDD 1 V/div;

Bottom Trace: OUT 1 V/div

Figure 15. Output Turn-on Response Time without a

Figure 16. Output Turn-on Response Time with a 1.1 nF

Capacitive Load and VDD=3.3V

Time: 500 µsec/div; Top Trace: VDD 2 V/div;

Bottom Trace: OUT 1 V/div

Figure 17. Output Turn-on Response Time without a

Figure 18. Output Turn-on Response Time with 1.1 nF

Capacitive Load and VDD=5V

10 Power Supply Recommendations

The LMT86's low supply current and supply range of 2.2V to 5.5V allow the device to easily be powered from

many sources.

Power supply bypassing is optional and is mainly dependent on the noise on the power supply used. In noisy

systems it may be necessary to add bypass capacitors to lower the noise that is coupled to the LMT86's output.

11 Layout

11.1 Layout Guidelines

The LMT86 is extremely simple to layout. If a power supply bypass capacitor is used it should be connected as

shown in the Layout Example.

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LMT86LP Datasheet(PDF) 15 Page - Texas Instruments