PCF5079 datasheet(6/28 Pages) PHILIPS

6 / 28 page

2001 Nov 21

Philips Semiconductors

Product speciﬁcation

Dual-band power ampliﬁer controller for

GSM, PCN and DCS

PCF5079

FUNCTIONAL DESCRIPTION

7.1

General

The PCF5079 contains an integrated amplifier for the

detected RF voltage from the sensor, an integrator and an

active filter to build up a PA control loop for cellular

systems with a small number of passive components

suitable for dual-band applications. The active band can

be selected by means of the dedicated input BS.

The sensor amplifier can amplify signals from an

RF power detector in a range of less than

−20 to +15 dBm.

This can comply to the PA output power range of

GSM900/1800/1900 systems when, for example, a

directional coupler with 20 dB attenuation is used for

GSM900 and a directional coupler with 18 dB attenuation

is used for GSM1800.

The external Schottky diodes for power detection (sensor)

are biased by an integrated current source of 30

µA.

Variations of the forward voltage with temperature have no

influence on the measured signal because they are

cancelled by the switched capacitor amplifier OP1.

An external DAC with at least 10-bit resolution (for

example, AUXDAC3 of baseband interface family

PCF5073x) is necessary to control the loop.

An integrated active filter smooths the voltage steps of the

DAC during ramp-up and ramp-down.

The operation principle is the same, independently of the

selected standard. The DAC signal and the sensor signal

are added by amplifier OP1. The voltage difference of both

signals is integrated by operational amplifier OP4

dedicated to the selected standard, which delivers the

PA control voltage on an external capacitance, CINT1 or

or CINT2, between pins VINT(N) and VCD or VCG,

respectively. The shape of the rising and falling power

burst edges can be determined by means of the DAC

voltage.

7.2

Power-up mode

The device includes a power-up input (pin PU) to switch

the IC on during time slots that are used in TDMA systems,

and to switch the IC off during the unused slots to reduce

current consumption.

7.3

OP4 (integrator)

The operational amplifier OP4 (integrator) consists of a

shared input stage, OP4IN and a dedicated output driver

for each standard, OP4G and OP4D. Depending on the

status of input BS, one driver is active and the other is kept

in power-down mode during active time slots.

7.4

Start-up and initial conditions

The PCF5079 is designed to operate in bursts, as required

in TDMA systems. Referring to Fig.4, for each time slot to

be transmitted the PCF5079 must be enabled by setting

signal PU to logic 1. Once pin PU is active, BS is taken

into account to allow correct initialisation of switches S1,

SFD,SFG, S3, S4 and S5, and of the configuration signals

PUG and PUD.

The feedback switch across the unused driver is kept open

and the output voltage from the unused driver is tied to VSS

to maintain the off state of the unused PA.

When pin PU is set to logic 1, at least 5

µs after VDD has

reached its final value, switches S1, the appropriate switch

SFD or SFG and S3 are closed, and switches S4 and S5

are opened. Because switch S1 is closed, the forward

voltage of Schottky diodes D1 and D2 is sampled on

capacitors C1 and C2 respectively.

Moreover, the control voltage on pin VCD or VCG is

initially forced to be at the pre-bias voltage because the

appropriate switch SFD or SFG and S3 are closed, and S4

is opened.

After a fixed time, defined on-chip, switch S1 is opened

and the circuit is ready.

Once switch S1 is open, a ramp signal applied at

pin VDAC (at least 20

µs after the transition of pin PU from

logic 0 to logic 1) with an amplitude of at least 70 mV, from

CODESTART to CODEKICK, determines the opening of

switch S3 and closing of switch S4 on the home voltage,

with a delay of 3

µs maximum with respect to the ramp.

After switch S3 opens (in a fixed amount of time), the

control voltage on pin VCD or pin VCG rises to the home

position to bias the PA to the beginning of the active range

of its control curve. During this time (typically 2

µs), the

appropriate switch SFD or SFG remains closed. When the

appropriate switch SFD or SFG is opened, switch S5 is

closed, allowing the transfer of any signal coming from

amplifier OP1. After this preset, the control voltage is free

to increase according to the control loop if the RF input is

enabled (see Fig.12).

For higher DAC ramp steps, the delay of switch S3

opening (S4 closing) is reduced while the delay between

switch SFD (SFG) opening with respect to S3 opening

(S4 closing) remains unchanged.

PCF5079 Datasheet(PDF) 6 Page - NXP Semiconductors

PCF5079 Datasheet(HTML) 6 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL