PCF5079 datasheet(9/28 Pages) PHILIPS

9 / 28 page

2001 Nov 21

Philips Semiconductors

Product speciﬁcation

Dual-band power ampliﬁer controller for

GSM, PCN and DCS

PCF5079

7.7

Considerations for ramp-down

Referring to Fig.5, the i-th code can be programmed to

have either the CODEEND or CODESTART value or any

code between, depending on the application preferences.

These codes do not produce any power at the output of the

PA, as CODESTART has been chosen to keep the PA

isolation. The proper conclusion of the ramp-down is

ensured by choosing CODEEND < CODESTART so that the

discharge of the integration capacitance is controlled until

the control voltage on pin VCD or VCG goes below the PA

conduction threshold and by applying at this time the PU

transition from logic 1 to logic 0.

At the beginning of a burst, the VDAC signal steps applied

at OP1 are not compensated by any signal at the sensor

input up to when pin VCD or VCG voltage is greater than

the PA conduction threshold voltage. In any case, the

initial DAC voltage steps are stored in the capacitance of

amplifier OP1. CODEEND has to be chosen so that the

energy inside the shaded zone cancels the energy

accumulated in the summing node (OP1) at the start of a

burst and not balanced by a feedback signal at the sensor

input.

The exact value of the energy required depends on the

specific PA, on the characteristics of the overall loop and

on the values chosen for the settable parameters inside

the loop.

A rough idea can be derived with a simplified analysis of a

ramp-up, ramp-down cycle using the following

simplifications:

• The starting conditions for OP1 and OP4 are biasing at

Vhome with zero charge on capacitances

• The initial rising of pin VCD or VCG voltage from Vhome

is caused only by the integration of the constant

CODEKICK

• VDAC is treated as applied directly at the summing

node, initially neglecting the transmission delay through

the internal low-pass filter.

Generally, the integrator OP4 input can be expressed as

(1)

where gs and gd are respectively the gains of sensor input

and DAC input in the summing amplifier OP1.

Equation (1) holds for closed loop operation. In the time

interval between the rising of pin VCD or VCG voltage due

to CODEKICK (t = 0) and when Vconduction for the PA is

reached (t = t1), ∆Vs is 0 and operation is open loop. In this

time interval, a charge accumulates in the summing node,

which remains uncompensated.

Time t1 can be calculated with the preceding simplification.

Now, to define the quantity

(2)

the current/voltage equations around the integrator OP4

can be solved by forcing the current through R1 to be

equal to the current through the integration capacitance

and calculating the

∆V generated on CINT, then

(3)

where

(4)

Substituting equation (4) into equation (3)

(5)

Under the hypothesis the voltage is constant:

(6)

Equation (6) can be used to calculate time t1 at which the

conduction of the PA is reached, considering that

(7)

(8)

Time t1 depends on the time constant of the integrator, by

the PA and by

∆VKICK. The condition to be fulfilled is that

the energy contained in the shaded zone (Fig.5) is at least

equal to the energy accumulated at the beginning:

(9)

where k is the number of quarter-bits during which

CODEEND is applied.

in integrator

()

∆V

VDAC

–

∆V

KICK

CODE

KICK

CODE

START

–

∆V

CINT

---------------

() τ

∫

()

∆V

KICK

-------------------------------

∆V

CINT

-----------------------------

∫

×∆V

KICK

∆V

CINT

-----------------------------

×∆V

KICK

home

∆V

CINT

conduction

⇒

CINT

conduction

home

–

∆V

KICK

-----------------------------------------------

out

OP1

(t) dt = k

CODE

END

CODE

START

–

()

∫

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