LM2657 datasheet(4/26 Pages) NSC

4 / 26 page

Pin Description (Continued)

Pin 21, V5: Upper rail of the lower FET drivers of both

channels. Also used to charge up the bootstrap capacitors of

the upper FET drivers. This is connected to an external 5V

supply. The 5V rail may be the same as the rail used to

provide power to the VDD pin (Pin 5). If these rails are

connected, the VDD pin must be well-decoupled so that it

does not interact with the V5 pin. A minimum 0.1µF (ceramic)

capacitor should be placed on the component side very

close to the IC with no intervening vias between this capaci-

tor and the V5/PGND pins.

Pin 22, VIN: The input that powers both the buck regulator

channels. It also is used by the internal ramp generator to

implement the line ‘feedforward’ feature. The VIN pin is also

used with the SENSE pin voltage to predict the CCM (con-

tinuous conduction mode) duty cycle and to thereby set the

minimum allowed DCM duty cycle to 85% of the CCM value

(in SKIP mode, see Pin 10). This is a high input impedance

pin, drawing only about 115µA from the input rail. A fault

condition will occur if this voltage drops below its UVLO

threshold.

Pin 23, LDRV1: LDRV pin of Channel 1. See Pin 20.

Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.

Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.

Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.

Pin 27, SW1: SW pin of Channel 1. See Pin 16.

Pin 28, ILIM1: Channel 1 Current Limit pin. See Pin 15.

LM2657 Datasheet(PDF) 4 Page - National Semiconductor (TI)