LM2657 datasheet(16/26 Pages) NSC

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Application Information (Continued)

MOSFET SELECTION

Selection of FETs for the controller must be done carefully

taking into account efficiency, thermal dissipation and drive

requirements. Typically the component selection is made

according to the most efficient FET for a given price.

When looking for a FET, it is often helpful to compose a

spreadsheet of key parameters. These parameters may be

summarized as on resistance (R

DS_ON), gate charge (QGS),

rise and fall times (t

r and tf). The power dissipated in a given

device may then be calculated according to the following

equations:

High side FET:

P= P

C +PGC +PSW

Where

C =Dx(IOUT

2 xR

DS_ON)

GC =5VxQGS xf

SW =0.5xVIN xIOUT x(tr +tf)xf

Low side FET:

P= P

C +PGC

Where

C =(1-D)x(IOUT

2 xR

DS_ON)

GC =5VxQGS xf

One will note that the gate charge requirements should be

low to ensure good efficiency. However, if a FET’s gate

charge requirement is too low (less than 8nC), the FET can

turn on spuriously. A good starting point for a 10A load is to

use a high side and low side FET each with an on resistance

of 5m

Ω (FET on resistance is a function of temperature,

therefore it is advisable to apply the appropriate correction

factor provided in the FET datasheet), gate to source charge

of 8nC (total gate charge of 36 nC), t

r = 11ns, tf = 47ns, and

temp coefficient of 1.4. For a 5V input and 1.2V/10A output (f

= 300kHz), this yields a power dissipation of 0.62 W (high

side FET) and 0.54 W (low side FET). The efficiency (Effi-

ciency

OUT/POUT

P_Low_Side_FET+P_High_Side_FET + V

IN *IQ)) is then

91%. While the same FET may be used for both the high

side and low side, optimal performance may not be realized.

CURRENT LIMIT RESISTOR

The timing scheme implemented in the LM2657 makes it

possible for the IC to continue monitoring an overcurrent

condition and to respond appropriately every cycle. This is

explained as follows:

Consider the LM2657 working under normal conditions, just

before an overload occurs. After the end of a given ON-pulse

(say ‘ton1’), the LM2657 starts sampling the current in the

low-side FET. This is the OFF-duration called ‘toff1’ in this

analysis. If an overcurrent condition is detected during this

OFF-duration ‘toff1’ the controller will decide to omit the next

ON-pulse (which would have occurred during the duration

‘ton2’). This is done by setting an internal ‘overcurrent latch’

which will keep HDRV low. The LDRV will now not only stay

high during the present OFF-duration (‘toff1’) but during the

duration of the next (omitted) ON-pulse (‘ton2’), and then as

expected also during the succeeding OFF-duration (‘toff2’).

But the ‘overcurrent latch’ is reset at the very start of the next

OFF-duration ‘toff2’. Therefore, if the overcurrent condition

persists, it can be recognized during ‘toff2’ and a decision to

skip the next ON-pulse (duration ‘ton3’) can be taken. Fi-

nally, several ON-pulses may get skipped until the current in

the lower FET falls below the current limit threshold.

Note that about 150ns after LDRV first goes high (start of

low-side conduction), the current monitoring starts. The peak

current seen by the current limit detector is slightly lower

than the peak inductor current.

To set the value of the current limiting resistor (RLIM, be-

tween ILIM pin and SW pin), the function of the ILIM pin must

be understood. Refer to Figure 8 to see how the voltage on

the ILIM pin changes as current ramps up.

For this analysis, the nominal value of current sourced (ILIM,

see Electrical Characteristics table) and the R

DS_ON of the

lower FET at 100˚C should be used. This will ensure ad-

equate headroom without the need for excessively large

components. For the chosen low-side FET of the high cur-

rent Evaluation board (Si4442DY), the typical R

DS_ON at

room temperature is 4.1m

Ω, but this is not to be used here.

The MAX FET R

DS_ON at room temperature is 5m

Ω. From

the datasheet, at 100˚C the R

DS_ON goes up typically 1.4

times. Therefore, the R

DS_ON to be used in the actual current

limit calculation is 1.4*5m

Ω =7mΩ.

Using I

ILIM = 62µA (see Electrical Characteristics table) and

Ω here will provide the lowest possible value of current

limit considering tolerances and temperature (for a given

RLIM resistor). This limit must be set higher than the actual

peak current in the converter under normal operation to

ensure that full rated power can be delivered under all con-

ditions by the converter without reaching the set current limit

value.

At the point where current limiting occurs (peak inductor

current becomes equal to current limit) the resistor for setting

the current limit can be calculated. The (peak) current limit

value depends on two factors:

a) The peak current in the inductor with the converter deliv-

ering maximum rated load. This should be calculated at

Vinmax.

b) The ‘overload margin’ (above maximum load) that needs

to be maintained. This will depend on the step loads likely to

be seen in the application and the response expected.

The peak inductor current under normal operation (maxi-

mum load) depends on the load and the inductance. It is

given by

where I

RIPPLE was determined in the output filter section.

Example: Let I

RIPPLE be 2A. The peak current under normal

operation is

20134719

FIGURE 8. Understanding Current Sensing

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