WM8524 datasheet(9/25 Pages) CIRRUS

Part #	WM8524

Description	24-bit 192kHz Stereo DAC with 2Vrms

PDF	25 Pages

Scroll/Zoom	100%

Manufacturer	CIRRUS [Cirrus Logic]

Direct Link	http://www.cirrus.com

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9 / 25 page

Production Data

WM8524

PD, Rev 4.1, October 2011

AUDIO INTERFACE TIMING – SLAVE MODE

BCLK

(input)

LRCLK

(input)

DACDAT

(input)

tDS

tDH

tLRH

tLRSU

tBCH

tBCL

tBCY

VIH

VIL

VIH

VIL

VIH

VIL

Figure 2 Digital Audio Data Timing – Slave Mode

Test Conditions

LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25

°C, Slave Mode

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

LRCLK set-up time to BCLK rising edge

tLRSU

LRCLK hold time from BCLK rising edge

tLRH

DACDAT hold time from LRCLK rising edge

tDH

DACDAT set-up time to BCLK rising edge

tDS

Table 1 Slave Mode Audio Interface Timing

Note:

BCLK period should always be greater than or equal to MCLK period.

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