WM8524

Production Data

w

PD, Rev 4.1, October 2011

10

POWER ON RESET CIRCUIT

Figure 3 Internal Power on Reset Circuit Schematic

The WM8524 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is used to

reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD

and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a

minimum threshold.

Figure 4 Typical Power Timing Requirements

Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

are in their default state and writes to the control interface may take place.

On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum