WM8804 datasheet(9/66 Pages) CIRRUS

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Production Data

WM8804

PD, Rev 4.5, March 2009

CONTROL INTERFACE – 3-WIRE MODE

CSB

SCLK

SDIN

tDHO

tDSU

tCSH

tSCY

SCS

LSB

SDO

tDL

LSB

CSS

CSU

tCSM

SCR

Figure 4 Control Interface Timing – 3-Wire Serial Control Mode

Test Conditions

PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK rising edge to CSB rising edge

tSCS

SCLK cycle time

tSCY

SCLK duty cycle

40/60

60/40

SDIN to SCLK set-up time

tDSU

SDIN hold time from SCLK rising edge

tDHO

SDOUT propagation delay from SCLK rising edge

tDL

CSB pulse width high

tCSH

SCLK to CSB low (required for read cycle) set-up time

tCSU

CSB min (write cycle only)

tCSM

0.5* tSCY

SCLK fall to CSB high

tCSR

CSB rising/falling to SCLK rising

tCSS

SCLK glitch suppression

tps

Table 4 Control Interface Timing – 3-Wire Serial Control Mode

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