Ver 1.0

Nov 09, 2000

TEL: 886-3-5788833

http://www.gmt.com.tw

5

G570

Global Mixed-mode Technology Inc.

Parameter Measurement Information

Figure 1. Test Circuits and Voltage Waveforms

Table of Timing Diagrams

Note:Data is clocked in on the positive leading edge of the clock. The latch should occur before the next

positive leading edge of the clock. For definition of D0 to D8, see the control logic table.

Figure 2. Serial-Interface Timing

V

DD

GND

50%

90%

t

off

t

on

10%

V

I(12V)

GND

LATCH

V

O(xVPP)

V

PP

C

L

VOLTAGE WAVEFORMS

LOAD CIRCUIT

V

DD

GND

50%

90%

t

off

t

on

10%

V

I(5V)

GND

LATCH

V

O(xVCC)

V

CC

C

L

VOLTAGE WAVEFORMS

LOAD CIRCUIT

D7

D8

D6

D5

D4

D3

D2

D1

D0

DATA

LATCH

CLOCK