M1040 datasheet(3/12 Pages) ICST

3 / 12 page

M1040 Datasheet Rev 0.1

3 of 12

Revised 11Nov2003

Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.i cst. com ● tel (508) 852-5400

M1040

VCSO BASED CLOCK PLL WITH AUTOSWITCH

Preliminar y In f o r m atio n

Integrated

Circuit

Systems, Inc.

DETAILED BLOCK DIAGRAM

Figure 3: Detailed Block Diagram

PLL DIVIDER SELECTION TABLES

M and R Divider Look-Up Tables (LUT)

The MR_SEL2:0 pins select the feedback and reference

divider values M and R to enable adjustment of loop

bandwidth and jitter tolerance. The look-up is defined in

Table 3.

M1040 M/R Divider LUT

Table 3

provides example Fin and phase detector

frequencies with 155.52MHz VCSO devices

(e.g., M1040-11-155.5200). See “Ordering Information”

on pg. 12

General Guidelines for M and R Divider Selection

General guidelines for M/R divider selection (see

following pages for more detail):

• A lower phase detector frequency should be used for

loop timing applications to assure PLL tracking,

especially during GR-253 jitter tolerance testing. The

recommended maximum phase detector frequency

for loop timing mode is 19.44MHz. The LOL pin should

not be used during loop timing mode.

• When LOL is to be used for system health monitoring,

the phase detector frequency should be 5MHz or

greater. Low phase detector frequencies make LOL

overly sensitive, and higher phase detector

frequencies make LOL less sensitive.

• The preceding guideline also applies when using the

AutoSwitch Mode, since AutoSwitch uses the LOL

output for clock fault detection.

Post-PLL Divider

The M1040 also features a post-PLL (P) divider for the

output clocks. It divides the VCSO frequency to produce

one of two selectable output frequencies (1/2 or 1/1 of

the VCSO frequency). That selected frequency appears

on both clock output pairs. The P_SEL pin selects the

value for the P divider.

Phase

Locked

Loop

(PLL)

M1040

SAW Delay Line

Phase

Shifter

VCSO

POST

nVC

POST

nOP_OUT

OP_OUT

POST

LOOP

OP_IN

nOP_IN

PLL

Phase

Detector

Loop Filter

Amplifier

External

Loop Filter

Components

MR_SEL2:0

Divider

MUX

REF_SEL

DIF_REF0

nDIF_REF0

M Divider

FOUT0

nFOUT0

P Divider

P_SEL

NBW

M / R Divider

LUT

DIF_REF1

nDIF_REF1

Auto

Ref Sel

LOL

Phase

Detector

REF_ACK

AUTO

INIT

LOL

FOUT1

nFOUT1

MR_SEL3:0

M Div R Div

Total

PLL

Ratio

Fin for

155.52MHz

VCSO (MHz)

Phase Det.

Freq. for

155.52MHz

VCSO (MHz)

0 0 0

19.44

0 0 1

19.44

2.43

0 1 0

77.76

0 1 1

77.76

9.72

1 0 0

155.52

1 0 1

155.52

19.44

1 1 0

Test Mode1

Note 1: Factory test mode; do not use.

N/A

1 1 1

0.25

622.08

77.76

Table 3: M1040 M/R Divider LUT

P_SEL

P Value

M1040-11-155.52

Output Frequency

(MHz)

77.76

155.52

Table 4: P Divider Selector Values and Frequencies

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