M1040 Datasheet Rev 0.1

8 of 12

Revised 11Nov2003

Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M1040

Preliminar y In f o r m atio n

Power-Up Initialization Function (INIT Pin)

The initialization function provides a short-term override

of the narrow bandwidth mode when the device is

powered up in order to facilitate phase locking.

NBW

initialization function puts the PLL into wide bandwidth

mode until eight consecutive phase detector cycles

occur without a single LOL event. Once the eight valid

PLL locked states have occurred, the PLL bandwidth is

automatically reduced to narrow bandwidth mode.

bandwidth mode unconditionally.

External Loop Filter

The M1040 requires the use of an external loop filter

components. These are connected to the provided filter

pins (see Figure 5).

Because of the differential signal path design, the

implementation consists of two identical

complementary RC filters as shown in

Figure 5.

Figure 5: External Loop Filter

PLL bandwidth is affected by the total “M” (feedback

divider) value, loop filter component values, and other

device parameters. See Table 6, Example External

Loop Filter Component Values, below.

PLL Simulator Tool Available

A free PC software utility is available on the ICS website

(www.icst.com). The M2000 Timing Modules PLL

Simulator is a downloadable application that simulates

PLL jitter and wander transfer characteristics. This

enables the user to set appropriate external loop

component values in a given application.

For guidance on device or loop filter implementa-

tion, contact CMBU (Commercial Business Unit)

Product Applications at (508) 852-5400.

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

OP_IN

nOP_IN

6

7

5

49

8

for M1040-yz-155.5200

Device Configuration

Example External Loop Filter Comp. Values

Nominal Performance Using These Values

F

REF

(MHz)

F

VCSO

(MHz)

MR_SEL2:0

MDiv NBW

R

LOOP

C

LOOP

R

POST

C

POST

PLL Loop

Bandwidth

Damping

Factor

Passband

155.52

0 0 0

8

0

6.8

k

Ω

10

µF

82

k

Ω

1000

pF

315

Hz

5.4

0.07

155.52

0 1 0

2

0

3.9

k

Ω

10

µF

33k

Ω

1000

pF

715

Hz

6.2

0.05

155.52

0 1 1

16

0

12

k

Ω

2.2

µF

82k

Ω

1000

pF

275

Hz

3.1

0.20

155.52

1 0 0

1

0

2.7

k

Ω

10

µF

47k

Ω

470

pF

980

Hz

6.0

0.05

155.52

1 0 1

8

0

5.6

k

Ω

4.7

µF

82k

Ω

1000

pF

260

Hz

3.0

0.20

Table 6: Example External Loop Filter Component Values

Note 1: K

and Passband Peaking. For PLL Simulator software, go to www.icst.com.

Note 2: Optimal for system clock filtering.

Note 3: Optimal for loop timing mode (LOL or Hitless Switching should not be used).