M1040 Datasheet Rev 0.1

4 of 12

Revised 11Nov2003

Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M1040

Preliminar y In f o r m atio n

The M1040 is a PLL (Phase Locked Loop) based clock

generator that generates two output clocks synchro-

nized to one of two selectable input reference clocks.

An internal high “Q” SAW delay line provides a low jitter

clock output.

A pin-selected look-up table is used to select the PLL

feedback divider (M Div) and reference divider (R Div)

as shown in Table 3 on pg. 3. The look-up table provides

flexibility in both the overall frequency multiplication

ratio (total PLL ratio) and phase detector frequency.

External loop filter component values influence the PLL

bandwidth, which is used to optimize jitter attenuation

characteristics.

The device features dual differential inputs with two

input selection modes: manual and automatic upon

clock failure. (The differential inputs are internally

configured for easy single-ended operation.)

NBW=0

to facilitate acquisition of phase lock).

An automatic input reselection feature, or “AutoSwitch”

is also included in the M1040. When the AutoSwitch

mode is enabled, the device will automatically switch to

the other reference clock input when the currently

selected reference clock fails. Reference selection is

non-revertive, meaning that only one reference

reselection will be made each time that AutoSwitch is

re-enabled.

In addition to the AutoSwitch feature, Hitless Switching

and Phase Build-out options can be ordered with the

device. The Hitless Switching and Phase Build-out

options help assure SONET/SDH MTIE and TDEV

compliance during either a manual or automatic input

reference reselection.

Hitless Switching (HS) provides a controlled output

clock phase change during a reference clock

reselection. HS is triggered by a Loss of Lock detection

by the PLL.

Input Reference Clocks

Two clock reference inputs and a selection mux are

provided. Either reference clock input can accept a

differential clock signal (such as LVPECL or LVDS) or

a single-ended clock input (LVCMOS or LVTTL on the

non-inverting input).

A single-ended reference clock on the unselected

reference input can cause an increase in output

clock jitter. For this reason, differential reference

inputs are preferred; interference from a differential

input on the non-selected input is minimal.

Implementation of single-ended input has been facili-

50k

Ω to Vcc and 50kΩ to ground. Figure 4 shows the

input clock structure and how it is used with either

LVCMOS / LVTTL inputs or a DC- coupled LVPECL

clock.

Figure 4: Input Reference Clocks

Differential Inputs

Differential LVPECL inputs are connected to both

reference input pins in the usual manner. The external

load termination resistors shown in Figure 4 (the 127

Ω

and 82

Ω resistors) will work for both AC and DC

coupled LVPECL reference clock lines. These provide

the 50

Single-ended Inputs

Single-ended inputs (LVCMOS or LVTTL) are

connected to the non-inverting reference input pin

In single-ended operation, when the unused inverting

input pin (nDIF_REF0 or nDEF_REF1) is left floating (not

connected), the input will self-bias at VCC/2.

MUX

0

REF_SEL

1

VCC

50k

50k

VCC

50k

50k

LVCMOS/

LVTTL

LVPECL

50k

50k

VCC

82

127

VCC

82

127

X

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω