M2021 datasheet(2/10 Pages) ICST

2 / 10 page

M2020/21 Datasheet Rev 1.0

2 of 10

Revised 30Jul2004

I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0

Integrated

Circuit

Systems, Inc.

M2020/21

VCSO BASED CLOCK PLL

Prod uct Data Sh eet

PIN DESCRIPTIONS

Number

Name

I/O

Configuration

Description

1, 2, 3, 10, 14, 26

GND

Ground

Power supply ground connections.

OP_IN

nOP_IN

Input

External loop filter connections.

See Figure 5, External Loop Filter, on pg. 6.

nOP_OUT

OP_OUT

Output

nVC

Input

11, 19, 33

VCC

Power

Power supply connection, connect to +3.3V.

FOUT1

nFOUT1

Output

No internal terminator

Clock output pair 1. Differential LVPECL.

FOUT0

nFOUT0

Output

No internal terminator

Clock output pair 0. Differential LVPECL.

P_SEL1

P_SEL0

P_SEL2

Input

Internal pull-down resistor1

Note 1: For typical values of internal pull-down and pull-UP resistors, see

DC Characteristics on pg. 8.

Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,

P Divider Look-Up Table (LUT), on pg. 3.

nDIF_REF1

Input

Biased to Vcc/2 2

Note 2: Biased toVcc/2, with 50k

Ω to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 8.

Reference clock input pair 1. Differential LVPECL or LVDS.

Resistor bias on inverting terminal supports TTL or LVCMOS.

DIF_REF1

Internal pull-down resistor1

REF_SEL

Input

Internal pull-down resistor1

Reference clock input selection. LVCMOS/LVTTL:

Logic 1 selects DIF_REF1, nDIF_REF1.

Logic 0 selects DIF_REF0, nDIF_REF0.

nDIF_REF0

Input

Biased to Vcc/2 2

Reference clock input pair 0. Differential LVPECL or LVDS.

Resistor bias on inverting terminal supports TTL or LVCMOS.

DIF_REF0

Internal pull-down resistor 1

FIN_SEL1

FIN_SEL0

Input

Internal pull-down resistor1

nput clock frequency selection. LVCMOS/LVTTL.

See Table 3, Mfin Divider Look-Up Table (LUT) on pg. 3.

MR_SEL0

MR_SEL1

Input

Internal pull-down resistor1

M and R divider value selection. LVCMOS/ LVTTL.

See Table 4, M and R Divider Look-Up Table (LUT) on pg. 3.

LOL

Output

Loss of Lock indicator output. Asserted when internal PLL is

not tracking the input reference for frequency and phase. 3

Logic 1 indicates loss of lock.

Logic 0 indicates locked condition.

Note 3: See LVCMOS Output in

DC Characteristics on pg. 8.

NBW

Input

Internal pull-UP resistor1

Narrow Bandwidth enable. LVCMOS/LVTTL:

Logic 1 - Narrow loop bandwidth, R

IN = 2100k

Ω.

Logic 0 - Wide bandwidth, R

IN = 100k

Ω.

34, 35, 36

DNC

Do Not Connect.

Internal nodes. Connection to these pins can cause erratic

device operation.

Table 2: Pin Descriptions

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