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M2021 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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M2021 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 10 page  M2020/21 Datasheet Rev 1.0 Revised 30Jul2004 Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0 M2020/21 VCSO BASED CLOCK PLL Integrated Circuit Systems, Inc. Product Data Sheet GENERAL DESCRIPTION The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5-10 GB data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M2020/21 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. FEATURES ◆ Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) ◆ Output frequencies of 15 to 700 MHz * ◆ LVPECL clock output (CML and LVDS options available) ◆ Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL ◆ Loss of Lock (LOL) output pin ◆ Narrow Bandwidth control input (NBW pin) ◆ Hitless Switching (HS) options with or without Phase Build-out (PBO) available for SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection ◆ Industrial temperature grade available ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package PIN ASSIGNMENT (9 x 9 mm SMT) Figure 1: Pin Assignment * Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM Figure 2: Simplified Block Diagram Example I/O Clock Frequency Combinations Using M2020-11-622.0800 or M2021-11-622.0800 Input Reference Clock (MHz) PLL Ratio (Pin Selectable) Output Clock (MHz) (M2020) (M2021) 19.44 or 38.88 (M2020) (M2021) 32 or 16 622.08 77.76 8 155.52 4 622.08 1 Table 1: Example I/O Clock Frequency Combinations M 2020 M 2021 ( T op View ) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND FIN_SEL0 MR_SEL0 MR_SEL1 LOL NBW VCC DNC DNC DNC M2020/21 Phase Detector FOUT0 nFOUT0 MR_SEL1:0 FIN_SEL1:0 R Div (1, 4, 16, 64) MUX 0 REF_SEL DIF_REF0 nDIF_REF0 1 Mfin Divider LUT Mfin Div (1, 4, 8, 32) or ( 1, 4, 8, 16) P_SEL2:0 DIF_REF1 nDIF_REF1 LOL VCSO Loop Filter TriState FOUT1 nFOUT1 P Divider LUT M Divider (1, 4, 16, 64) NBW 2 3 P Divider FOUT0: 1, 4, 8, 32 or TriState FOUT1: 1, 4, 8 or TriState 2 M / R Divider LUT M2020/21 VCSO Based Clock PLL |
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