M2020/21 Datasheet Rev 1.0

5 of 10

Revised 30Jul2004

M2020/21

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

In normal phase-locked condition, the instantaneous

phase error is measured by the phase detector and is

converted to charge pump current pulses. These

current pulses are then integrated by the external loop

filter to create a VCSO control voltage. The loop filter

acts as a low pass filter to remove unwanted reference

clock jitter above a determined frequency or PLL

bandwidth. For reference phase jitter frequencies within

the loop bandwidth, phase jitter amplitude is passed on

to the output clock according to the PLL loop frequency

response curve.

The relationship between the nominal VCSO center

frequency (Fvcso), the M divider, and the input

reference frequency (Fin) is:

The M, R, and Mfin dividers can be set by pin configura-

FIN_SEL0

.

Post-PLL Divider

The M2020/21 also features a post-PLL (P) divider.

Through use of the P divider, the device’s output

frequency (Fout) can be that of the VCSO (such as

622.08MHz

(common optical reference clocks in SONET and SDH

systems).

Table 5 on pg. 3.)

Accounting for the P divider, the complete relationship

between the input clock reference frequency (Fin) and

output clock frequency (Fout) is defined as:

Due to the narrow tuning range of the VCSO (+120ppm

guaranteed), appropriate selection of all of the following

are required for the PLL be able to lock: VCSO center

frequency, input frequency, and divider selections.

TriState

The TriState feature puts the LVPECL output driver into

a high impedance state, effectively disconnecting the

of the clock net is then set to 50

Ω by the external circuit

resistors. (This is in distinction to a CMOS output in

TriState, in which case the net goes to a high

impedance and the logic value floats.) The 50

Ω

impedance level of the LVPECL TriState allows

manufacturing In-circuit Test to drive the clock net with

an external 50

Ω generator to validate the integrity of

clock net and the clock load.

Any unused output (single-ended or differential) should

be left unconnected (floating) in system application.

This minimizes output switching current and therefore

minimizes noise modulation of the VCSO.

Narrow Bandwidth (NBW) Control Pin

included to enable adjustment of the PLL loop

internal resistor Rin is 100k

2100k

Ω. This lowers the loop bandwidth by a factor of

about 21 (2100 / 100) and lowers the damping factor by

about 4.6 (the square root of 21), assuming the same

external loop filter component values.

Loss of Lock Indicator (LOL) Output Pin

Under normal device operation, when the PLL is locked,

circumstances when the VCSO cannot fully phase lock

to the input (as measured by a greater than 4 ns

discrepancy between the feedback and reference clock

when the phase detector error is less than 2 ns. The

loss of lock indicator is a low current LVCMOS output.

Guidelines for Using LOL

In a given application, the magnitude of peak-to-peak

jitter at the phase detector will usually increase as the R

an unusual clock condition, or a clock fault, the

MR_SEL1:0

pins should be set to provide a phase detector

frequency is equal to Fin divided by the R divider).

be used when the device is used in a loop timing

application.

Example Frequency and Divider Combinations

Using M2021-yz-622.0800

Fvcso =

Fin

x

Mfin x M/R

622.08

38.88

16 x (1/1, 4/4, etc.)

77.76

8 x (1/1, 4/4, etc.)

155.52

4 x (1/1, 4/4, etc.)

622.08

1 x (1/1, 4/4, etc.)

Table 6: Example I/O Clock Frequency Combinations

Fvcso

Fin

Mfin

×

M

R

----

×

=

Fout

Fvcso

P

-------------------

=

Fin

MMfin

×

RP

×

--------------------------

×

=