M2021 datasheet(4/10 Pages) ICST

4 / 10 page

M2020/21 Datasheet Rev 1.0

4 of 10

Revised 30Jul2004

I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0

Integrated

Circuit

Systems, Inc.

M2020/21

VCSO BASED CLOCK PLL

Prod uct Data Sh eet

FUNCTIONAL DESCRIPTION

The M2020/21 is a PLL (Phase Locked Loop) based

clock generator that generates output clocks synchro-

nized to one of two selectable input reference clocks.

An internal high "Q" SAW delay line provides low jitter

signal performance and establishes the output

frequency of the VCSO (Voltage Controlled SAW

Oscillator). In a given M2020/21 device, the VCSO

center frequency is fixed. A common center frequency

is 622.08MHz, for SONET for SDH optical network

applications. The VCSO center frequency is specified at

time of order (see “Ordering Information” on pg. 10).

The VCSO has a guaranteed tuning range of

±120 ppm

(commercial temperature grade).

Pin selectable dividers are used within the PLL and

for the output clock. This enables tailoring of device

functionality and performance. The Mfin divider controls

the overall PLL multiplication ratio and thus determines

the input reference clock (see Table 3, on pg. 3). The

M and R dividers control the phase detector frequency

(see Table 4). The P divider scales the VCSO output

enabling lower output frequency selections (Table 5).

The M2020/21 includes a Loss of Lock (LOL) indicator,

which provides status information to system

management software. A Narrow Bandwidth (NBW)

control pin is provided as an additional mechanism for

adjusting PLL loop bandwidth without affecting the

phase detector frequency.

Options are available for Hitless Switching (HS) with or

without Phase Build-out (PBO). They provide

SONET/SDH MTIE and TDEV compliance during a

reference clock reselection.

Allowance for a single-ended input has been facilitated

by a unique input resistor bias scheme, which is

described next and shown in Figure 4.

Input Reference Clocks

Two clock reference inputs and a selection mux are

provided. Either reference clock input can accept a

differential clock signal (such as LVPECL or LVDS) or

a single-ended clock input (LVCMOS or LVTTL on the

non-inverting input).

A single-ended reference clock on the unselected

reference input can cause an increase in output

clock jitter. For this reason, differential reference

inputs are preferred; interference from a differential

input on the non-selected input is minimal.

Configuration of a single-ended input has been

facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,

with 50k

Ω to Vcc and 50kΩ to ground. The input clock

structure, and how it is used with either

LVCMOS/LVTTL inputs or a DC- coupled LVPECL

clock, is shown in Figure 4.

Figure 4: Input Reference Clocks

Differential Inputs

Differential LVPECL inputs are connected to both

reference input pins in the usual manner. The external

load termination resistors shown in Figure 4 (the 127

Ω

and 82

Ω resistors) is ideally suited for both AC and DC

coupled LVPECL reference clock lines. These provide

the 50

Ω load termination and the VTT bias voltage.

Single-ended Inputs

Single-ended inputs (LVCMOS or LVTTL) are

connected to the non-inverting reference input pin

(DIF_REF0 or DIF_REF1). The inverting reference input pin

(nDIF_REF0 or nDIF_REF1) must be left unconnected.

In single-ended operation, when the unused inverting

input pin (nDIF_REF0 or nDEF_REF1) is left floating (not

connected), the input will self-bias at VCC/2.

PLL Operation

The M2020/21 is a complete clock PLL. It uses a phase

detector and configurable dividers to synchronize the

output of the VCSO with the selected reference clock.

The PLL will work correctly, meaning it will phase-lock

the VCSO output to the input reference clock, when the

internal phase detector inputs are able to run at the

same frequency. This means the PLL dividers must be

set appropriately and a suitable reference frequency

must be chosen for the intended output frequency.

When the PLL is not set up appropriately, the VCSO is

forced to its upper or lower operating limit which is

typically about 250 ppm above or below the VCSO

center frequency (no more than 500 ppm above or

below).

MUX

REF_SEL

VCC

50k

VCC

50k

LVCMOS/

LVTTL

LVPECL

50k

VCC

127

VCC

127

M2020/21

DIF_REF0

nDIF_REF0

DIF_REF1

nDIF_REF1

Ω

M2021 Datasheet(PDF) 4 Page - Integrated Circuit Systems

M2021 Datasheet(HTML) 4 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10

Datasheet Download

Link URL