M2020/21 Datasheet Rev 1.0

9 of 10

Revised 30Jul2004

M2020/21

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

Output Rise and Fall Time

Figure 6: Output Rise and Fall Time

Output Duty Cycle

Figure 7: Output Duty Cycle

AC Characteristics

Unless stated otherwise, V

LVPECL outputs terminated with 50

Ω to V

Symbol Parameter

Min

Typ

Max

Unit Conditions

F

IN

Input Frequency

DIF_REF0, nDIF_REF0,

DIF_REF1, nDIF_REF1

10

700

MHz

F

OUT

Output Frequency

FOUT0, nFOUT0, FOUT1, nFOUT1

15

700

MHz

APR

VCSO Absolute

Pull-Range

Commercial

ppm

Industrial

ppm

PLL Loop

Note 1: Parameters needed for PLL Simulator software; see Table 7, Example Values for Loop Filter External Components, on pg. 7.

K

VCO

VCO Gain

800

kHz/V

R

IN

Internal Loop Resistor

Wide Bandwidth

100

k

Ω

Narrow Bandwidth

2100

k

Ω

BW

VCSO

VCSO Bandwidth

700

kHz

Phase Noise

and Jitter

Φn

Single Side Band

Phase Noise

1

kHz Offset

38.88 MHz

Mfin=32 or 16,

M=1, R=1

10

kHz Offset

dBc/Hz

100

kHz Offset

dBc/Hz

J(t)

Jitter (rms)

12

0.25

0.5

ps

50

0.25

0.5

ps

odc

Note 2: See Parameter Measurement Information on pg. 9.

P = 4, 8, or 32

45

50

55

%

P = 1

40

50

60

%

t

R

FOUT0, nFOUT0, FOUT1, nFOUT1

200

450

500

ps

20

t

F

FOUT0, nFOUT0, FOUT1, nFOUT1

200

450

500

ps

20

Table 11: AC Characteristics

20%

80%

20%

80%

Clock Output

V

P

nFOUT

FOUT

t

PW

t

PERIOD

(Output Pulse Width)

odc =