Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

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5

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PDALL = 0, all channels

active

257

295

PDALL = 0, all channels

active, DT = 1

257

PDALL = 0, 1 channel active

82

PDALL = 0, PD[3:0] = 1111

23

mA

19.3MHz at

-0.5dBFS

PDALL = 1, global power

down, PD[3:0] =1111, no

clock input

300

µA

PDALL = 0, all channels

active

56

65

PDALL = 0, all channels

active, DT = 1

72

PDALL = 0, 1 channel active

42

PDALL = 0, PD[3:0] = 1111

37

mA

19.3MHz at

-0.5dBFS

PDALL = 1, global power-

down, PD[3:0] =1111, no

clock input

375

µA

diodes on CLK input, Figure 2

0mA

Power Dissipation

563

648

mW

TIMING CHARACTERISTICS (Note 6)

Data Valid to CLKOUT Rise/Fall

24)

- 0.15

24

24)

+ 0.15

ns

CLKOUT Output Width High

Figure 5

12

ns

CLKOUT Output Width Low

Figure 5

12

ns

FRAME Rise to CLKOUT Rise

Figure 4 (Note 7)

24)

- 0.15

24

24)

+ 0.15

ns

Sample CLK Rise to Frame Rise

Figure 4 (Notes 7 and 8)

2)

+0.9

2)

+1.3

2)

+1.7

ns