5

ICS94222

Advance Information

This document is confidential and should not be released

without written consent from ICS.

1.

Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to

byte 8.

2.

When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written

but not 15, neither byte 14 or 15 will load into the receiver.

3.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

4.

The input is operating at 3.3V logic levels.

5.

The data byte format is 8 bit bytes.

6.

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been

transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.

The data is loaded until a Stop sequence is issued.

7.

At power-on, all registers are set to a default condition, as shown.

Notes:

Brief I

Programmable System Frequency Generator

R egister N ame

Byte

D escrip tion

PW D D efault

Functionality & Frequency

Select Register

0

O utput frequency, hardw are / I

frequency select, spread spectrum &

output enable control register.

See individual

byte description

O utput Control Registers

1-6

A ctive / inactive output control

registers/latch inputs read back.

See individual

byte description

V endor ID & Revision ID

Registers

7

Byte 11 bit[7:4] is ICS vendor id - 1001.

Other bits in this register designate device

revision ID of this part.

See individual

byte description

Byte Count

Read Back Register

8

Writing to this register w ill configure

byte count and how many byte w ill be

Watchdog Control Registers

9 Bit [6:0]

Watchdog enable, w atchdog status and

programmable 'safe' frequency' can be

configured in this register.

000,0000

V CO Control Selection Bit

9 Bit [7]

This bit select w hether the output

frequency is control by hardw are/byte 0

configurations or byte 11&12

programming.

0

Watchdog Timer

Count Register

10

Writing to this register w ill configure the

number of seconds for the w atchdog

timer to reset.

V CO Frequency Control

Registers

11-12

These registers control the dividers ratio

into the phase detector and thus control

the V CO output frequency.

D epended on

hardw are/byte 0

configuration

Spread Spectrum Control

Registers

13-14

These registers control the spread

percentage amount.

D epended on

hardw are/byte 0

configuration

G roup Skew s Control

Registers

15-16

Increment or decrement the group skew

amount as compared to the initial skew .

See individual

byte description

O utput Rise/Fall Time

Select Registers

17-20

These registers w ill control the output

rise and fall time.

See individual

byte description