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ICS94222

Advance Information

This document is confidential and should not be released

without written consent from ICS.

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS94222. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP#

is synchronized by the ICS94222 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least

10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on

latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94222 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the ICS94222.

3. All other clocks continue to run undisturbed.

4. CPU_STOP# is shown in a high (true) state.