MPC7450EC datasheet(38/52 Pages) MOTOROLA

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MPC7450 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

1.9.2

PLL Power Supply Filtering

The AVDD power signal is provided on the MPC7450 to provide power to the clock generation PLL. To

ensure stability of the internal clock, the power supplied to the AVDD input signal should be ﬁltered of any

noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in

Figure 20 using surface mount capacitors with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby

circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery

of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the

inductance of vias.

Figure 20. PLL Power Supply Filter Circuit

1.9.3

Power Supply Voltage Sequencing

The notes in Table 2 contain cautions about the sequencing of the external bus voltages and core voltage of

the MPC7450 (when they are different). These cautions are necessary for the long-term reliability of the

part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and

excessive current can ﬂow through these diodes. If the system power supply design does not control the

voltage sequencing, the circuit shown in Figure 21 can be added to meet these requirements. The 30BF10

5502

275

220

183

157

138

110

6002

300

240

200

171

150

120

100

6502

325

260

217

186

163

130

108

6662

333

266

222

190

167

133

111

7002

350

280

233

200

175

140

117

7332

367

293

244

209

183

147

122

Notes:

1. The core and L3 frequencies are for reference only. Some examples may represent core or L3 frequencies which

are not useful, not supported, or not tested for the MPC7450; see Section 1.5.2.3, “L3 Clock AC Speciﬁcations,” for

valid L3_CLK frequencies. (Shaded cells do not comply with Table 10.)

2. These core frequencies are not supported by all speed grades; see Table 8.

Table 17. Sample Core-to-L3 Frequencies (continued)

Core Frequency (MHz)

÷2

÷2.5

÷3

÷3.5

÷4

÷5

÷6

VDD

AVDD

Ω

2.2 µF

GND

Low ESL Surface Mount Capacitors

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

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