MPC7450EC datasheet(26/52 Pages) MOTOROLA

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MPC7450 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 11 shows the typical connection diagram for the MPC7450 interfaced to PB2 SRAMs, such as the

Motorola MCM63R737, or Late Write SRAMs, such as the Motorola MCM63R836A.

Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface

L3_ADDR[0:17]

L3_CNTL[0]

SA[0:17]

SW,

SRAM 0

DQ[0:17]

DQ[18:36]

L3_CNTL[1]

GVDD/2

GND

SBWa, SBWb,

SBWc, SBWd

SRAM 1

GVDD/2

GND

{L3_DATA[0:15],

{L3_DATA[16:31],

{L3_DATA[32:47],

L3_CLK[0]

L3_CLK[1]

L3_ECHO_CLK[0]

L3_ECHO_CLK[1]

L3_ECHO_CLK[2]

{L3_DATA[48:63],

L3_DP[0:1]}

L3_DP[2:3]}

L3_DP[4:5]}

L3_DP[6:7]}

Denotes

Receive (SRAM

to MPC7450)

Aligned Signals

MPC7450

Denotes

Transmit

(MPC7450 to

SRAM)

Aligned Signals

L3_ECHO_CLK[3]

SA[0:17]

SW,

DQ[0:17]

DQ[18:36]

SBWa, SBWb,

SBWc, SBWd

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

MPC7450EC Datasheet(PDF) 26 Page - Motorola, Inc

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