Electronic Components Datasheet Search
  English  ▼

X  

MPC7450EC Datasheet(PDF) 24 Page - Motorola, Inc

Part # MPC7450EC
Description  Freescale Semiconductor, Inc.
PDF  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MPC7450EC Datasheet(HTML) 24 Page - Motorola, Inc

Back Button MPC7450EC Datasheet HTML 20Page - Motorola, Inc MPC7450EC Datasheet HTML 21Page - Motorola, Inc MPC7450EC Datasheet HTML 22Page - Motorola, Inc MPC7450EC Datasheet HTML 23Page - Motorola, Inc MPC7450EC Datasheet HTML 24Page - Motorola, Inc MPC7450EC Datasheet HTML 25Page - Motorola, Inc MPC7450EC Datasheet HTML 26Page - Motorola, Inc MPC7450EC Datasheet HTML 27Page - Motorola, Inc MPC7450EC Datasheet HTML 28Page - Motorola, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 52 page
background image
24
MPC7450 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 10 shows the L3 bus timing diagrams for the MPC7450 interfaced to MSUG2 SRAMs.
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
1.5.2.4.2
L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs are synchronous to the MPC7450; one L3_CLKn signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signal it received. The MPC7450 needs a copy of that delayed clock which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7450 inputs
L3_ECHO_CLK0 and L3_ECHO_CLK2 respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are
phase-aligned with the input clock received at the SRAMs. The MPC7450 will latch the incoming data on
the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 13 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
assuming the timing relationships of Figure 12 and the loading of Figure 8.
L3_ECHO_CLK[0,1,2,3]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
Parity Inputs
L3_CLK[0,1]
ADDR, L3CNTL
VM
tL3CHOV
tL3CHOX
VM
L3DATA WRITE
tL3CHOZ
VM
VM
VM
VM
tL3CHDV
tL3CHDX
VM
VM
VM
Outputs
Inputs
tL3CLDV
tL3CLDX
tL3CLDZ
tL3DVEH
tL3DXEL
tL3DVEL
tL3DXEH
Note: tL3DVEH and tL3DVEL as drawn here will be negative numbers, i.e., input setup time will be
time after the clock edge.
Note: tL3CHDV and tL3CLDV as drawn here will be negative numbers, i.e., output valid time will be
time before the clock edge.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
INC
.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com