11

Preliminary

On Board Clock Generation

The ES521 Evaluation System has a pair of jumper selectable oscillators. Please refer to the

datasheet for details of operating modes.

There are three clocks supplied to the 5216s:

MCLK – The main clock straight from the oscillator.

SCK – Bit clock used for I

WS – Word sync / Frame sync used by I

PCM mode uses the 13.824MHz oscillator to generate an 8kHz signal commonly used in telecom

applications. The clock jumper(J9) must be set to the 13.824MHz setting and CODEC jumper (J1)

must be set to PCM. The clock generator allows short and long frame sync to be selected.

Note: The frame sync setting is not part of the configuration registers and therefore applies to

both devices. It is not stored in the paths setup.

I

length setting. The CODEC jumper(J9) must be in the I

Running One Or Two Devices

The Demo Board is set up to allow running either one of the two devices from the PC parallel

port, and the central bank of DIP switches allows decoupling of the I

the devices can be controlled independently.

The headers bring out the full I

device. In the normal mode with the DIP switches on, the devices are connected together

allowing the CODECs of both devices to communicate with each other, and the PC to control the

I

chip to be connected.

If the external CODEC is connected to the main 5216, the external CODEC will be in slave mode,

if connected to the secondary 5216, the clocks from the clock generator on the Demo Board can

be disconnected and the secondary 5216 run in slave mode.