LAN91C100FD datasheet(24/68 Pages) SMSC

24 / 68 page

SMSC DS – LAN91C100FD REV. B

Page 24

Rev. 05/31/2000

BANK 0

OFFSET

NAME

TYPE

SYMBOL

MEMORY CONFIGURATION

Lower Byte -

READ/WRITE

Upper Byte -

READ ONLY

MCR

HIGH

BYTE

MEMORY SIZE MULTIPLIER

LOW

BYTE

MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)

MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve memory to be used

later for transmit, limiting the amount of memory that receive packets can use. When programmed for zero, the memory

allocation between transmit and receive is completely dynamic. When programmed for a non-zero value, the allocation is

dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free

memory is less or equal to the programmed value. This register defaults to zero upon reset. It is not affected by the RESET

MMU command.

The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE. If the

memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with

transmit allocations) the CPU should update the value of this register after allocating or releasing memory.

The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory

Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256

*2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when

the entire memory is being reserved for transmit (i.e., low byte of MCR = FFh).

BANK1

OFFSET

NAME

TYPE

SYMBOL

CONFIGURATION REGISTER

READ/WRITE

The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-time.

This register is part of the EEPROM saved setup.

HIGH

BYTE

MII

SELECT

NO WAIT

FULL

STEP

AUI

SELECT

LOW

BYTE

Reserved

INT SEL1

INT SEL0

MII SELECT - Used to select the network interface port. When set, the LAN91C100FD will use its MII port and interface a

PHY device at the nibble rate. When clear, the LAN91C100FD will use its 10 Mbps ENDEC interface. This bit drives the MII

SEL pin. Switching between ports should be done with transmitter and receiver disabled and no transmit/receive packets in

progress.

NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not

ready for a transfer. When clear, negates IOCHRDY for two to three clocks on any cycle to the LAN91C100FD.

LAN91C100FD Datasheet(PDF) 24 Page - SMSC Corporation

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