Signal 1

GND Plane

Power Plane

Signal 2

15

TMUX136

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SCDS367A – AUGUST 2017 – REVISED OCTOBER 2017

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10 Power Supply Recommendations

TI recommends placing a bypass capacitor as close to the supply pin VCC as possible to help smooth out lower

frequency noise to provide better load regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the high

speed traces.

The high-speed signalpaths must should be no more than 4 inches long; otherwise, the eye diagram

performance may be degraded.

Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points on twisted pair

lines; through-hole pins are not recommended.

When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching

regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.

Avoid stubs on the high-speed signals traces because they cause signal reflections. If a stub is unavoidable, then

the stub must be less than 200 mm.

Route all high-speed signal traces over continuous GND planes, with no interruptions.

Avoid crossing over anti-etch, commonly found with plane splits.

Due to high frequencies, a printed circuit board with at least four layers is recommended; two signal layers

separated by a ground and power layer as shown in Figure 26.

Figure 26. Four-Layer Board Stack-Up

The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must

be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power

plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the

number of signal vias reduces EMI by reducing inductance at high frequencies.