LTC3830ES datasheet(8/24 Pages) LINER

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LTC3830/LTC3830-1

sn3830 3830fs

TEST CIRCUITS

FREQSET

COMP

IMAX

SHDN

VCC

VSHDN VCC

PVCC2 PVCC1

PVCC

IFB

6800pF

3830 F02

GND

PGND

SENSE–

LTC3830

SENSE+

COMP

VCOMP

VFB

IFB

VCC

PVCC1

PVCC2

6800pF

0.1

µF

6800pF

G1 RISE/FALL

G2 RISE/FALL

3830 F03

IMAX

GND

PGND

LTC3830

Figure 2

Figure 3

APPLICATIO S I FOR ATIO

OVERVIEW

The LTC3830 is a voltage mode feedback, synchronous

switching regulator controller (see Block Diagram) de-

signed for use in high power, low voltage step-down

(buck) converters. It includes an onboard PWM generator,

a precision reference trimmed to

±0.8%, two high power

MOSFET gate drivers and all necessary feedback and

control circuitry to form a complete switching regulator

circuit. The PWM loop nominally runs at 200kHz.

The 16-lead versions of the LTC3830 include a current

limit sensing circuit that uses the topside external N-channel

power MOSFET as a current sensing element, eliminating

the need for an external sense resistor.

Also included in the 16-lead version and the LTC3830-1

is an internal soft-start feature that requires only a single

external capacitor to operate. In addition, 16-lead parts

feature an adjustable oscillator that can free run or

synchronize to external signal with frequencies from

100kHz to 500kHz, allowing added flexibility in external

component selection. The 8-lead version does not in-

clude current limit, internal soft-start and frequency

adjustability. The LTC3830-1 does not include current

limit, frequency adjustability, external synchronization

and the shutdown function.

THEORY OF OPERATION

Primary Feedback Loop

The LTC3830/LTC3830-1 sense the output voltage of the

circuit at the output capacitor and feeds this voltage back

to the internal transconductance error amplifier, ERR,

through a resistor divider network. The error amplifier

compares the resistor-divided output voltage to the inter-

nal 1.265V reference and outputs an error signal to the

PWM comparator. This error signal is compared with a

fixed frequency ramp waveform, from the internal oscil-

lator, to generate a pulse width modulated signal. This

PWM signal drives the external MOSFETs through the G1

and G2 pins. The resulting chopped waveform is filtered by

LO and COUT which closes the loop. Loop compensation is

achieved with an external compensation network at the

COMP pin, the output node of the error amplifier.

MIN, MAX Feedback Loops

Two additional comparators in the feedback loop provide

high speed output voltage correction in situations where

the error amplifier may not respond quickly enough. MIN

compares the feedback signal to a voltage 40mV below the

internal reference. If the signal is below the comparator

threshold, the MIN comparator overrides the error ampli-

fier and forces the loop to maximum duty cycle, >91%.

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