LTC3830ES datasheet(18/24 Pages) LINER

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LTC3830/LTC3830-1

sn3830 3830fs

Table 3 shows the suggested compensation component

values for 5V to 3.3V applications based on 470

µF Sanyo

POSCAP 4TPB470M output capacitors.

Table 3. Recommended Compensation Network for 5V to 3.3V

Applications Using Multiple Paralleled 470

µF Sanyo POSCAP

4TPB470M Output Capacitors

L1 (

µH)

COUT (µF)

RC (kΩ)CC (nF)

C1 (pF)

1.2

1410

6.8

4.7

1.2

2820

2.2

1.2

4700

2.2

2.4

1410

2.4

2820

2.2

2.4

4700

2.2

4.7

1410

4.7

2820

4.7

4700

150

Table 4 shows the suggested compensation component

values for 5V to 3.3V applications based on 1500

µF Sanyo

MV-WX output capacitors.

Table 4. Recommended Compensation Network for 5V to 3.3V

Applications Using Multiple Paralleled 1500

µF Sanyo MV-WX

Output Capacitors

L1 (

µH)

COUT (µF)

RC (kΩ)CC (nF)

C1 (pF)

1.2

4500

1.5

120

1.2

6000

1.2

9000

0.47

2.4

4500

2.4

6000

2.4

9000

0.47

4.7

4500

100

3.3

4.7

6000

150

0.47

4.7

9000

200

0.47

LAYOUT CONSIDERATIONS

When laying out the printed circuit board, use the follow-

ing checklist to ensure proper operation of the LTC3830.

These items are also illustrated graphically in the layout

diagram of Figure 11. The thicker lines show the high

current paths. Note that at 10A current levels or above,

current density in the PC board itself is a serious concern.

Traces carrying high current should be as wide as pos-

sible. For example, a PCB fabricated with 2oz copper

requires a minimum trace width of 0.15" to carry 10A.

1. In general, layout should begin with the location of the

power devices. Be sure to orient the power circuitry so that

a clean power flow path is achieved. Conductor widths

should be maximized and lengths minimized. After you are

satisfied with the power path, the control circuitry should

be laid out. It is much easier to find routes for the relatively

small traces in the control circuits than it is to find

circuitous routes for high current paths.

2. The GND and PGND pins should be shorted directly at

the LTC3830. This helps to minimize internal ground dis-

turbances in the LTC3830 and prevent differences in ground

potential from disrupting internal circuit operation. This

connection should then tie into the ground plane at a single

point, preferably at a fairly quiet point in the circuit such as

close to the output capacitors. This is not always practical,

however, due to physical constraints. Another reasonably

good point to make this connection is between the output

capacitors and the source connection of the bottom

MOSFET Q2. Do not tie this single point ground in the trace

run between the Q2 source and the input capacitor ground,

as this area of the ground plane will be very noisy.

APPLICATIO S I FOR ATIO

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