LTC3830ES datasheet(9/24 Pages) LINER

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LTC3830/LTC3830-1

sn3830 3830fs

APPLICATIO S I FOR ATIO

Similarly, the MAX comparator forces the output to 0%

duty cycle if the feedback signal is greater than 40mV

above the internal reference. To prevent these two com-

parators from triggering due to noise, the MIN and MAX

comparators’ response times are deliberately delayed by

two to three microseconds. These two comparators help

prevent extreme output perturbations with fast output

load current transients, while allowing the main feedback

loop to be optimally compensated for stability.

Thermal Shutdown

The LTC3830/LTC3830-1 have a thermal protection cir-

cuit that disables both gate drivers if activated. If the chip

junction temperature reaches 150

°C, both G1 and G2 are

pulled low. G1 and G2 remain low until the junction

temperature drops below 125

°C, after which, the chip

resumes normal operation.

Soft-Start and Current Limit

The 16-lead LTC3830 devices include a soft-start circuit

that is used for start-up and current limit operation. The

LTC3830-1 only has the soft-start function; the current

limit function is disabled. The 8-lead LTC3830 has both the

soft-start and current limit function disabled. The SS pin

requires an external capacitor, CSS, to GND with the value

determined by the required soft-start time. An internal

µA current source is included to charge CSS. During

power-up, the COMP pin is clamped to a diode drop (B-E

junction of QSS in the Block Diagram) above the voltage at

the SS pin. This prevents the error amplifier from forcing

the loop to maximum duty cycle. The LTC3830/LTC3830-1

operate at low duty cycle as the SS pin rises above 0.6V

(VCOMP ≈ 1.2V). As SS continues to rise, QSS turns off and

the error amplifier takes over to regulate the output. The

MIN comparator is disabled during soft-start to prevent it

from overriding the soft-start function.

The 16-lead LTC3830 devices include yet another feed-

back loop to control operation in current limit. Just before

every falling edge of G1, the current comparator, CC,

samples and holds the voltage drop measured across the

external upper MOSFET, Q1, at the IFB pin. CC compares

the voltage at IFB to the voltage at the IMAX pin. As the peak

current rises, the measured voltage across Q1 increases

due to the drop across the RDS(ON) of Q1. When the voltage

at IFB drops below IMAX, indicating that Q1’s drain current

has exceeded the maximum level, CC starts to pull current

out of CSS, cutting the duty cycle and controlling the output

current level. The CC comparator pulls current out of the

SS pin in proportion to the voltage difference between IFB

and IMAX. Under minor overload conditions, the SS pin

falls gradually, creating a time delay before current limit

takes effect. Very short, mild overloads may not affect the

output voltage at all. More significant overload conditions

allow the SS pin to reach a steady state, and the output

remains at a reduced voltage until the overload is re-

moved. Serious overloads generate a large overdrive at

CC, allowing it to pull SS down quickly and preventing

damage to the output components. By using the RDS(ON)

of Q1 to measure the output current, the current limiting

circuit eliminates an expensive discrete sense resistor that

would otherwise be required. This helps minimize the

number of components in the high current path.

The current limit threshold can be set by connecting an

external resistor RIMAX from the IMAX pin to the main VIN

supply at the drain of Q1. The value of RIMAX is determined

by:

RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX

where:

ILMAX = ILOAD + (IRIPPLE/2)

ILOAD = Maximum load current

IRIPPLE = Inductor ripple current

= ()(

)

()()( )

OUT

OSC

–

fOSC = LTC3830 oscillator frequency = 200kHz

LO = Inductor value

RDS(ON)Q1 = On-resistance of Q1 at ILMAX

IIMAX= Internal 12µA sink current at IMAX

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