LTC3830ES datasheet(7/24 Pages) LINER

7 / 24 page

LTC3830/LTC3830-1

sn3830 3830fs

PI FU CTIO S

FREQSET (Pin 11/NA/NA): Frequency Set. Use this pin to

adjust the free-running frequency of the internal oscillator.

With the pin floating, the oscillator runs at about 200kHz.

A resistor from FREQSET to ground speeds up the oscil-

lator; a resistor to VCC slows it down.

IMAX (Pin 12/NA/NA): Current Limit Threshold Set. IMAX

sets the threshold for the internal current limit compara-

tor. If IFB drops below IMAX with G1 on, the LTC3830 goes

into current limit. IMAX has an internal 12µA pull-down to

GND. Connect this pin to the main VIN supply at the drain

of Q1, through an external resistor to set the current limit

threshold. Connect a 0.1

µF decoupling capacitor across

this resistor to filter switching noise.

IFB (Pin 13/NA/NA): Current Limit Sense. Connect this pin

to the switching node at the source of Q1 and the drain of

Q2 through a 1k resistor. The 1k resistor is required to

prevent voltage transients from damaging IFB.This pin is

used for sensing the voltage drop across the upper

N-channel MOSFET, Q1.

VCC (Pin 14/Pin 7/Pin 7): Power Supply Input. All low

power internal circuits draw their supply from this pin.

Connect this pin to a clean power supply, separate from

the main VIN supply at the drain of Q1. This pin requires a

4.7

µF bypass capacitor. The LTC3830-1 and the 8-lead

LTC3830 have VCC and PVCC2 tied together at Pin 7 and

require a 10

µF bypass capacitor to GND.

PVCC2 (Pin 15/Pin 7/Pin 7): Power Supply Input for G2.

Connect this pin to the main high power supply.

G2 (Pin 16/Pin 8/Pin 8): Bottom Gate Driver Output.

Connect this pin to the gate of the lower N-channel

MOSFET, Q2. This output swings from PGND to PVCC2. It

remains low when G1 is high or during shutdown mode.

To prevent output undershoot during a soft-start cycle, G2

is held low until G1 first goes high. (FFBG in Block

Diagram.)

BLOCK DIAGRA

–

PVCC1

PVCC2

PGND

SENSE+

VREF

VREF – 3%

VREF + 3%

18k

11.2k

SENSE–

3830 BD

POR

FFBG

ENABLE

PWM

QSS

VREF

VREF – 3%

VREF + 3%

MAX

MIN

ERR

µA

INTERNAL

OSCILLATOR

100

µs DELAY

SHDN

FREQSET

COMP

POWER DOWN

DISABLE GATE DRIVE

LOGIC AND

THERMAL SHUTDOWN

–

µA

IMAX

IFB

VCC

GND

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