Preliminary Technical Data

AD4002/AD4006/AD4010

Rev. PrA | Page 7 of 36

TIMING SPECIFICATIONS

See Figure 2 for the timing voltage levels.

Table 2. Digital Interface Timing

Parameter

Symbol

Min

Typ

Max

Unit

CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE

270

290

320

ns

ACQUISITION PHASE1

AD4002

290

ns

AD4006

790

ns

AD4010

1790

ns

TIME BETWEEN CONVERSIONS

AD4002

500

ns

AD4006

1000

ns

AD4010

2000

ns

CNV PULSE WIDTH (CS MODE)2

10

ns

SCK PERIOD (CS MODE)3

VIO > 2.7 V

9.8

ns

VIO > 1.7 V

12.3

ns

SCK PERIOD (DAISY-CHAIN MODE)4

VIO > 2.7 V

20

ns

VIO > 1.7 V

25

ns

SCK LOW TIME

3

ns

SCK HIGH TIME

3

ns

SCK FALLING EDGE TO DATA REMAINS VALID DELAY

1.5

ns

SCK FALLING EDGE TO DATA VALID DELAY

VIO > 2.7 V

7.5

ns

VIO > 1.7 V

10.5

ns

CNV OR SDI LOW TO SDO D17 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE)

VIO > 2.7 V

10

ns

VIO > 1.7 V

13

ns

CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY

190

ns

LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY5

60

ns

CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)

20

ns

SDI VALID SETUP TIME FROM CNV RISING EDGE

2

ns

SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)

2

ns

SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE)

12

ns

SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)

2

ns

SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)

2

ns

1

The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the

AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010.

2

3

A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable

throughput for different modes of operation.

4

A 50% duty cycle is assumed for SCK.

5

1

FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.

SPECIFICATIONS IN TABLE 1.

Figure 2. Voltage Levels for Timing