AD4002 datasheet(31/36 Pages) AD

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Preliminary Technical Data

AD4002/AD4006/AD4010

Rev. PrA | Page 31 of 36

CS MODE, 4-WIRE TURBO MODE

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host.

It provides additional time during the end of the ADC conversion

process to clock out the previous conversion result, giving a

lower SCK rate. The AD4002 can achieve a throughput rate of

2 MSPS only when turbo mode is enabled and using a minimum

SCK rate of 75 MHz. With turbo mode enabled, the AD4006

can also achieve its maximum throughput rate of 1 MSPS with a

minimum SCK rate of 25 MHz, and the AD4010 can achieve its

maximum throughput rate of 500 kSPS with a minimum SCK

rate of 11 MHz.

The connection diagram is shown in Figure 56, and the

corresponding timing diagram is shown in Figure 57.

AD4002/

AD4006/

AD4010

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

VIO

1kΩ

CS1

Figure 56. CS Mode, 4-Wire Turbo Mode Connection Diagram

This mode replaces the 4-wire with busy indicator mode by

programming the turbo mode bit, Bit 1 (see Table 14).

With SDI high, a rising edge on CNV initiates a conversion.

The previous conversion data is available to read after the CNV

rising edge. The user must wait tQUIET1 time after CNV is

brought high before bringing SDI low to clock out the previous

conversion result. The user must also wait tQUIET2 time after the

last falling edge of SCK to when CNV is brought high.

When the conversion is complete, the AD4002/AD4006/AD4010

enter the acquisition phase and power down. The ADC result

can be read by bringing its SDI input low, which consequently

outputs the MSB onto SDO. The remaining data bits are then

clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can capture the data, a

digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18th SCK

falling edge or when SDI goes high (whichever occurs first),

SDO returns to high impedance.

ACQUISITION

SDO

SCK

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

tCYC

tSCK

tSCKL

tEN

tHSDO

tDSDO

tDIS

tSCKH

D17

D16

D15

tQUIET1

tQUIET2

tACQ

CONVERSION

tCONV

Figure 57. CS Mode, 4-Wire Turbo Mode Timing Diagram

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