AD4002 datasheet(24/36 Pages) AD

24 / 36 page

AD4002/AD4006/AD4010

Preliminary Technical Data

Rev. PrA | Page 24 of 36

TBD

Figure 44. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C

The AD4002/AD4006/AD4010 power down automatically at

the end of each conversion phase; therefore, the power scales

linearly with the sampling rate. This feature makes the device

ideal for low sampling rates (even a few samples per second)

and battery-powered applications. Figure 45 shows the AD4002/

AD4006/AD4010 total power dissipation and individual power

dissipation for each rail.

TBD

Figure 45. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 1.8 V,

VREF = 5 V, 25°C

DIGITAL INTERFACE

Although the AD4002/AD4006/AD4010 have a reduced

number of pins, they offer flexibility in their serial interface

modes. The AD4002/AD4006/AD4010 can also be programmed

via 16-bit SPI writes to the configuration registers.

When in CS mode, the AD4002/AD4006/AD4010 are compatible

with SPI, QSPI™, MICROWIRE®, digital hosts, and digital signal

processors (DSPs). In this mode, the AD4002/AD4006/AD4010

can use either a 3-wire or 4-wire interface. A 3-wire interface

using the CNV, SCK, and SDO signals minimizes wiring con-

nections, which is useful, for instance, in isolated applications.

A 4-wire interface using the SDI, CNV, SCK, and SDO signals

allows CNV, which initiates the conversions, to be independent of

the readback timing (SDI). This interface is useful in low jitter

sampling or simultaneous sampling applications.

The AD4002/AD4006/AD4010 provide a daisy-chain feature

using the SDI input for cascading multiple ADCs on a single

data line, similar to a shift register.

The mode in which the device operates depends on the SDI

level when the CNV rising edge occurs. CS mode is selected if

SDI is high, and daisy-chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, daisy-chain mode is always selected.

In either 3-wire or 4-wire mode, the AD4002/AD4006/AD4010

offer the option of forcing a start bit in front of the data bits.

This start bit can be used as a busy signal indicator to interrupt

the digital host and trigger the data reading. Otherwise, without a

busy indicator, the user must time out the maximum conversion

time prior to readback.

The busy indicator feature is enabled in CS mode if CNV or SDI

is low when the ADC conversion ends.

The state of SDO on power-up is either low or high-Z, depending

on the states of CNV and SDI, as shown in in Table 11.

Table 11. State of SDO on Power-Up

CNV

SDI

SDO

Low

High-Z

The AD4002/AD4006/AD4010 have turbo mode capability in

both 3-wire and 4-wire mode. Turbo mode is enabled by writing

to the configuration register and replaces the busy indicator

feature when enabled. Turbo mode allows a slower SPI clock rate,

making interfacing simpler. The maximum throughput of

2 MSPS for the AD4002 can be achieved only with turbo mode

enabled and a minimum SCK rate of 75 MHz.

The SCK rate must be sufficiently fast to ensure the conversion

result is clocked out before another conversion is initiated. The

minimum required SCK rate for an application can be derived

based on the sample period (tCYC), the number of bits that must

be read (including data and optional status bits), and which

digital interface mode is used. Timing diagrams and explanations

for each digital interface mode are given in the digital modes of

operation sections (see the CS Mode, 3-Wire Turbo Mode

section through the Daisy-Chain Mode section).

Status bits can also be clocked out at the end of the conversion

data if the status bits are enabled in the configuration register.

There are six status bits in total, as shown in Table 15.

The AD4002/AD4006/AD4010 are configured by 16-bit SPI

writes to the desired configuration register. The 16-bit word can

be written via the SDI line while CNV is held low. The 16-bit

word consists of an 8-bit header and 8-bit register data. For

isolated systems, the ADuM141D is recommended, which can

support the 75 MHz SCK rate required to run the AD4002 at its

full throughput of 2 MSPS.

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