PC107A datasheet(33/50 Pages) ATMEL

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PC107A [Preliminary]

2137C–HIREL–03/04

Table 16 provides the two-wire interface output AC timing specifications for the PC107A.

At recommended operating conditions (see Table 3 on page 12) with GV

DD = 3.3V ± 5%

and LV

DD = 3.3 ±0.3V

Notes:

1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.

2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency

Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified

SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA sig-

nals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The

resulting delay value is added to the value in the table (where this note is referenced). See Figure 19 on page 34.

3. Since SCL and SDA are open-drain type outputs, which the PC107A can only drive low, the time required for SCL or SDA to

reach a high level depends on external signal capacitance and pull-up resistor values.

4. Specified at a nominal 50 pF load.

5. D

FDR is the decimal divider number indexed by FDR[5:0] value. Refer to the two-wire Interface chapter’s Serial Bit Clock Fre-

quency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a variable

number that would make the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal to a vari-

able number that would make the result of the divide (Data Hold Time value) equal to a number less than 9.

Figure 18. Two-wire Interface Timing Diagram II

Table 16. Two-wire Interface Output AC Timing Specifications

Num

Characteristics

Min

Max

Unit

Notes

Start condition hold time

(FDR[5] == 0)

× (D

FDR/16) / 2N +

(FDR[5] == 1)

× (D

FDR/16) / 2M

–CLKs

(1)(2)(5)

Clock low period

DFDR / 2

–

CLKs

(1)(2)(5)

SCL/SDA rise time (from 0.5V to 2.4V)

–

(3)

Data hold time

8.0 + (16

× 2FDR[4:2]) × (5 -

4({FDR[5],FDR[1]} == b’10) -

3({FDR[5],FDR[1]} == b’11) -

2({FDR[5],FDR[1]} == b’00) -

1({FDR[5],FDR[1]} == b’01))

–CLKs

(1)(2)(5)

SCL/SDA fall time (from 2.4V to 0.5V)

–

< 5

(4)

Clock high time

DFDR / 2

–

CLKs

(1)(2)(5)

Data setup time (PC107A as a master only)

FDR / 2) - (Output data hold time)

–

CLKs

(1)(5)

Start condition setup time (for repeated start

condition only)

DFDR + (Output start condition hold

time)

–CLKs

(1)(2)(5)

Stop condition setup time

4.0

–

CLKs

(1)(2)

SCL

SDA

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