SI5010 datasheet(11/16 Pages) ETC

11 / 16 page

Si5010

Preliminary Rev. 0.31

Differential Input Circuitry

The Si5010 provides differential inputs for both the high

speed data (DIN) and the reference clock (REFCLK)

inputs. An example termination for these inputs is

shown in Figure 8. In applications where direct DC

coupling is possible, the 0.1

µF capacitors may be

omitted. The DIN and REFCLK input amplifiers require

an input signal with a minimum differential peak-to-peak

voltage listed in Table 2 on page 6.

Differential Output Circuitry

The Si5010 utilizes a current mode logic (CML)

architecture

output

both

the

recovered

clock

(CLKOUT) and data (DOUT). An example of output

termination with AC coupling is shown in Figure 9. In

applications in which direct DC coupling is possible, the

0.1

µF capacitors may be omitted. The differential

peak-to-peak voltage swing of the CML architecture is

listed in Table 2 on page 6.

Figure 8. Input Termination for DIN and REFCLK (AC Coupled)

Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)

Differential

Driver

Si5010

0.1

µ F

0.1

µ F

Zo = 50

Ω

Zo = 50

Ω

DIN+,

REFC LK +

DIN–,

REFC LK –

2.5 k

Ω

2.5 k

Ω

10 k

Ω

10 k

Ω

102

Ω

VDD

GND

DOUT–,

CLKOUT–

Ω

0.1

µ F

0.1

µ F

Zo = 50

Ω

Zo = 50

Ω

Si5010

VDD

100

Ω

100

Ω

VDD

DOUT+,

CLKOUT+

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