SI5010 datasheet(13/16 Pages) ETC

13 / 16 page

Si5010

Preliminary Rev. 0.31

12, 13

DOUT–,

DOUT+

OCML

Differential Data Output.

The data output signal is a retimed version of the

data recovered from the signal present on DIN. It is

phase aligned with CLKOUT and is updated on the

rising edge of CLKOUT.

PWRDN/CAL

LVTTL

Power Down.

To shut down the high-speed outputs and reduce

power consumption, hold this pin high. For normal

operation, hold this pin low.

Calibration.

To initiate an internal self-calibration, force a

high-to-low transition on this pin. (See "PLL

Self-Calibration" on page 9.)

Note: This input has a weak internal pulldown.

16, 17

CLKOUT–,

CLKOUT+

OCML

Differential Clock Output.

The output clock is recovered from the data signal

present on DIN. In the absence of data, the output

clock is derived from REFCLK.

RATESEL

LVTTL

Data Rate Select.

This pin configures the onboard PLL for clock and

data recovery at one of two user selectable data

rates. See Table 7 for configuration settings.

Note: This input has a weak internal pulldown.

No Connect.

This pin should be tied to ground.

Table 8. Si5010 Pin Descriptions (Continued)

Pin #

Pin Name

I/O

Signal Level

Description

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